Parallel Erase and Sequential Verify for NAND Memory Blocks
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Solution Overview
Problem
Traditional memory devices face inefficiencies in performing operations such as erasing multiple blocks, leading to increased execution times and reduced performance, particularly in NAND memory systems, due to sequential processing and high latency.
Innovation Solution
Implementing firmware algorithms that enable parallel erase operations and sequential verification for multiple blocks, allowing for simultaneous erasure and subsequent verification, which reduces overall erase time and improves memory system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential erase operations are performed on multiple memory blocks, then verification reliability is ensured, but erase time increases significantly
Solution Approach 1:
The patent segments the verification process from the erase operation. Multiple blocks are erased simultaneously in parallel, while verification is performed separately on a per-block basis after the parallel erase completes. This segmentation allows the erase operation to benefit from parallelism while verification maintains its required reliability through individual block checking.
Solution Approach 2:
The patent performs preliminary parallel erasure of multiple blocks before conducting sequential verification. By completing all erase operations first in parallel, the system establishes the erased state across all blocks, then subsequently verifies each block individually to ensure reliability. This preliminary action approach separates the time-critical erase phase from the verification phase.
2Loss of time
If parallel erase operations are implemented for multiple blocks, then erase time is reduced, but device complexity increases
Solution Approach 1:
The patent merges multiple erase operations into a single parallel execute command that simultaneously erases multiple specified blocks. Instead of requiring separate erase commands for each block, the system combines them into one unified operation, reducing the number of command cycles needed while maintaining parallel execution capability.
Solution Approach 2:
The patent implements a universal parallel erase command structure that can handle variable numbers of blocks (2-32 blocks) through a single command format. The command includes block address fields and a block count field, allowing the same command mechanism to adapt to different erase scenarios without requiring multiple specialized commands.
3Productivity
If multiple blocks are erased simultaneously, then productivity is improved, but synchronization difficulty across die increases
Solution Approach 1:
The patent incorporates verification feedback after parallel erase operations. Each block is individually verified to confirm successful erasure, and the system can identify and re-erase specific blocks that failed verification. This feedback mechanism ensures synchronization and reliability across all blocks erased in parallel, allowing the system to handle multi-die environments with varying erase characteristics.
Data Source
AI summary
A variety of applications can include memory systems that have one or more memory devices capable of performing memory operations on multiple blocks of memory in response to a command from a host. For example, improvement in erase performance can be attained by erasing multiple blocks of memory by one of a number of approaches. Such approaches can include parallel erasure followed by serial verification in response to a single command. Other approaches can include sequential erase and verify operations of the multiple blocks in response to a single command. Additional apparatus, systems, and methods are disclosed.