Parallel Error-Correction Branches for Multiple-Bit Memory Errors
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Solution Overview
Problem
Existing error detection methods are inefficient in detecting and correcting multiple-bit errors, leading to potential undetected or uncorrectable errors in data stored in memory cells.
Innovation Solution
A device and method utilizing two error processing branches with syndrome generators, error detection units, and error correction units that process data words with differing bits, allowing parallel processing and decision-making based on corrected or uncorrected data words to enhance error detection and correction efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single error processing branch is used, then the device complexity is low, but the reliability of error detection and correction is insufficient
Solution Approach 1:
The error processing system is divided into multiple independent error processing branches (first and second branches), each capable of independently processing data words with different bit configurations. This segmentation allows parallel error detection and correction operations, improving reliability without requiring a single complex processing unit.
Solution Approach 2:
The patent introduces a new dimension of error processing by creating multiple branches that process data words differing in at least one bit. This dimensional expansion from a single processing path to multiple parallel paths enables more comprehensive error detection and correction capabilities.
2Productivity
If traditional error correction methods are used, then the processing speed is acceptable, but the detection of multiple-bit errors is inefficient
Solution Approach 1:
The system performs preliminary error detection and correction in parallel across multiple branches before final decision-making. By preparing corrected data words in advance through multiple independent correction paths, the system accelerates the overall error correction process while improving multiple-bit error detection capability.
Solution Approach 2:
The decision unit receives feedback from multiple error processing branches and uses this information to select the most reliable corrected data word. The feedback mechanism allows the system to compare results from different branches and make informed decisions, improving both speed and reliability of error correction.
Data Source
AI summary
The approaches proposed here relate to error processing by means of at least two error processing branches. Each of the error processing branches is configured (i) to process a data word, wherein the data words of the error processing branches differ in at least one bit, and (ii) to provide a processed data word to a decision unit. The decision unit is configured to select one of the processed data words or to perform a predetermined action if an uncorrectable error has been detected.