Parallel Error Correction Coding for Low-Latency Multilevel Symbols
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Solution Overview
Problem
High-speed optical transmission systems face challenges in increasing transmission capacity and distance while maintaining low latency and reducing circuit scale, particularly in metro-core optical transmission systems where error correction coding schemes for multilevel modulation symbols are inefficient due to increased circuit complexity and latency.
Innovation Solution
An error correction coding apparatus that processes m bits×n symbols in parallel, replacing known bits with parity bits generated by an error correction coding circuit, allowing for efficient error correction coding and decoding with reduced circuit complexity and low latency, using a selector to output either information or parity bits based on the error correction code sequence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If error correction coding is performed for each bit sequence of multilevel modulation symbols in parallel, then processing speed is improved, but circuit scale increases
Solution Approach 1:
The bit sequence is divided into multiple groups, with known bits segmented and placed in specific positions. This segmentation allows the error correction coding circuit to process only the necessary unknown bits while maintaining parallel processing capability, thus improving speed without proportionally increasing circuit scale.
Solution Approach 2:
A single error correction coding circuit is designed to handle multiple functions: it processes both known bits (for positioning and error detection) and unknown bits (for actual error correction). This multi-functionality eliminates the need for separate circuits for different bit sequences, reducing overall circuit scale while maintaining high processing speed.
2Reliability
If powerful error correction codes are applied to increase transmission capacity and distance, then transmission performance is improved, but latency increases
Solution Approach 1:
Known bits are pre-positioned in the bit sequence before error correction coding is applied. This preliminary arrangement allows the decoding process to quickly identify and utilize these reference bits, accelerating the error correction process and reducing latency while maintaining the powerful error correction capability needed for long-distance transmission.
Solution Approach 2:
Known bits serve as intermediary reference points within the bit sequence, enabling the error correction circuit to efficiently process unknown bits without examining every bit sequentially. This intermediary structure reduces the computational complexity and time required for error correction, thereby reducing latency.
3Reliability
If known bits are assigned to specific bit sequences and error correction coding is performed, then error correction capability is improved, but circuit complexity increases
Solution Approach 1:
The known bits are extracted and separated from the unknown bits in the bit sequence. This extraction allows the error correction coding circuit to focus only on processing the unknown bits while using the known bits as reference, thereby reducing circuit complexity while maintaining strong error correction capability.
Solution Approach 2:
The known bits within the bit sequence serve themselves as reference points for the error correction process. The error correction circuit uses these self-provided reference bits to automatically identify and correct errors in the unknown bits, eliminating the need for external control mechanisms and reducing circuit complexity.
Data Source
AI summary
An error correction coding apparatus that performs error correction coding using, as an error correction code sequence, a frame of m bits×n symbols input in m-bit parallel, where m and n are positive integers, includes: an error correction coding circuit that performs error correction coding using, as information bits, m bits×n symbols including known bits assigned to a bit sequence specified in the error correction code sequence and generate error correction coded parity bits; and a selector that replaces the known bits of the error correction code sequence with the parity bits.