Parallel Error-Position Arithmetic Circuit for NAND Flash ECC
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Solution Overview
Problem
The size of the arithmetic circuit for decoding error correction codes, particularly in memory systems like NAND flash, increases significantly due to methods such as the Chien search, which sequentially substitutes values into the error locator polynomial to find error positions, leading to high latency.
Innovation Solution
Implementing a parallelized arithmetic circuit with a matrix calculator and evaluators that calculate matrices corresponding to affine polynomials derived from error locator polynomials, reducing complexity by applying affine decomposition to the error position calculator, thereby parallelizing the substitution processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the Chien search method is used to calculate error positions by sequentially substituting values into the error locator polynomial, then the error position can be found, but the circuit size increases and latency is high
Solution Approach 1:
The patent applies segmentation by dividing the error locator polynomial into multiple affine polynomials based on the code length n. Each affine polynomial is evaluated separately by different evaluators, breaking down the large sequential substitution task into smaller parallel segments. This reduces the circuit size required for each individual evaluator while maintaining the ability to find all error positions.
Solution Approach 2:
The patent transitions from sequential substitution in one dimension (time) to parallel evaluation in multiple dimensions by using p evaluators that simultaneously process different affine polynomials. This dimensional change allows multiple substitutions to occur in parallel, reducing latency while keeping individual circuit units smaller.
2Measurement precision
If the Chien search method is used to calculate error positions by sequentially substituting values into the error locator polynomial, then the error position can be found, but the decoding latency increases
Solution Approach 1:
The error locator polynomial is segmented into multiple affine polynomials that can be evaluated in parallel. By dividing the polynomial evaluation task across p evaluators, the patent reduces the total time required to find all error positions, directly addressing the latency issue while preserving detection accuracy.
Solution Approach 2:
The patent performs preliminary decomposition of the error locator polynomial into affine polynomials before the actual error position search. This preprocessing step enables subsequent parallel evaluation, reducing the time required for the main error position detection task and thereby reducing overall decoding latency.
3Productivity
If parallel evaluation is implemented with multiple evaluators, then the substitution processing is parallelized and latency is reduced, but the circuit complexity increases
Solution Approach 1:
The patent segments the polynomial evaluation task into p independent evaluators, each handling a specific affine polynomial. This segmentation allows parallel processing that improves productivity while keeping each individual evaluator's circuit complexity manageable, as each evaluator only needs to handle a portion of the total computation.
Solution Approach 2:
The patent designs evaluators with universal functionality that can process different affine polynomials using the same structural framework. This multi-functionality allows the system to achieve parallel processing capability without proportionally increasing circuit complexity, as the same evaluator architecture is reused across multiple parallel units.
Data Source
AI summary
According to one embodiment, an arithmetic circuit includes a matrix calculator and p or more evaluators. The matrix calculator calculates a matrix that corresponds to a linearized polynomial included in an affine polynomial obtained by decomposing an error locator polynomial. Each of the evaluators calculates a first multiplication result obtained by multiplying the matrix by a first multiplication value based on a substitution value to be substituted into the error locator polynomial, calculates, for each of one or more evaluation terms that are different from the linearized polynomial, a second multiplication result obtained by multiplying a second multiplication value based on the substitution value by a corresponding evaluation term, and outputs error position information based on a value obtained by adding the first multiplication result and the second multiplication result.