Parallel Fault Simulator with Back-Propagation for IC Verification

The patent segments the fault analysis process into two distinct phases: (1) a fast parallel simulation phase that provides preliminary fault detection using simplified models, and (2) a targeted gate-level timing simulation phase that focuses computational resources only on suspicious or critical fault locations identified in the first phase. This segmentation resolves the contradiction by maintaining high measurement precision through the second phase while dramatically reducing overall simulation time through the efficiency of the first phase.

The patent performs preliminary fault screening using parallel simulation techniques before conducting detailed gate-level timing simulations. By executing a preliminary analysis that identifies likely fault locations and characteristics, the system prepares the subsequent detailed simulation phase to focus only on relevant areas, thereby maintaining accurate fault detection while minimizing the time consumed by comprehensive gate-level simulations.

The patent divides the verification process into a fast parallel simulation stage that handles the entire circuit efficiently, and a selective gate-level timing simulation stage that focuses only on critical paths and suspicious fault locations. This segmentation allows the system to maintain high manufacturing precision for complex designs with many gates while improving productivity by avoiding exhaustive simulation of the entire circuit.

The patent applies partial action by performing gate-level timing simulations only on selected critical portions of the circuit rather than the entire design. The parallel simulation phase provides sufficient coverage for most faults, and gate-level simulations are applied partially only where needed to confirm suspicions or analyze critical paths, thereby maintaining verification accuracy while significantly improving throughput for large-scale designs.

The patent merges multiple simulation objectives into a unified parallel simulation framework that simultaneously performs fault injection, fault propagation, and diagnostic analysis in a single simulation run. By combining these functions that would traditionally require separate simulation runs, the system maintains high reliability through comprehensive fault detection while dramatically reducing the total time required compared to sequential approaches.

The patent implements continuous useful action by maintaining active fault propagation and diagnostic analysis throughout the entire simulation process without interruption. The parallel simulation architecture allows multiple fault scenarios to be evaluated concurrently and continuously, eliminating the need to stop and restart simulations between different analysis phases, thereby improving both reliability and time efficiency.