Parallel RS FEC Interleaving for Low-Latency Burst Error Protection
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Solution Overview
Problem
Traditional block interleavers in wired communication systems introduce latency and require significant memory buffers, making them unsuitable for high-data-rate applications, where they also necessitate parallel processing of multiple encoders operating at slower speeds.
Innovation Solution
The implementation of a low-cost, low-latency interleaving physical layer (PHY) system that omits the use of memory buffers and allows RS FEC encoders to operate at a lower frequency, achieving 100% throughput by distributing error bursts across multiple shorter FEC codes, thereby reducing latency and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional block interleavers are used to protect against burst errors, then error protection capability is improved, but latency increases and memory buffer requirements increase
Solution Approach 1:
The patent divides the traditional single long FEC code into multiple shorter FEC codes by segmenting the data stream. Each shorter code processes a portion of the data, allowing parallel processing and reducing the time each code needs to operate, thereby reducing latency while maintaining error protection capability through the distributed structure
Solution Approach 2:
The patent introduces a new dimensional approach by using multiple parallel FEC code paths instead of a single sequential path. This dimensional change from one long processing chain to multiple shorter parallel chains enables simultaneous error protection across different data segments, reducing overall processing latency
2Reliability
If traditional block interleavers are used to protect against burst errors, then error protection capability is improved, but device complexity and cost increase due to memory buffer requirements
Solution Approach 1:
The patent extracts and removes the memory buffer component from the traditional block interleaver architecture. By using multiple shorter FEC codes that process data in parallel without requiring centralized buffering, the design eliminates the need for large memory buffers while maintaining the ability to protect against burst errors through distributed coding
Solution Approach 2:
By segmenting the data into multiple streams processed by separate FEC codes, the patent distributes the processing load and eliminates the need for a centralized memory buffer to hold entire blocks of data, thereby reducing device complexity and memory requirements
3Reliability
If longer RS FEC codes are used to handle extended error bursts, then error protection capability is improved, but encoder and decoder complexity increase
Solution Approach 1:
The patent segments the protection task across multiple shorter FEC codes rather than using a single long code. Each shorter code has reduced complexity in its encoder and decoder operations, while the collective system maintains robust error protection capability through the parallel structure
Solution Approach 2:
Instead of using one long code that provides excessive protection for each individual data segment, the patent applies partial protection through multiple shorter codes, each handling a portion of the data. This distributed approach reduces the complexity burden on individual encoders and decoders while achieving comparable or superior overall protection
4Reliability
If traditional block interleavers are used for high data rate communication, then error protection is provided, but throughput is limited due to sequential processing requirements
Solution Approach 1:
The patent segments the data stream into multiple parallel channels, each processed by independent FEC codes. This segmentation enables simultaneous processing of multiple data portions, increasing overall throughput while maintaining error protection capability across the entire data stream
Solution Approach 2:
The patent merges multiple parallel FEC processing paths into a unified output stream. By combining the results from multiple shorter codes processed in parallel, the system achieves high throughput comparable to or exceeding traditional single-code approaches while maintaining robust error protection
Data Source
AI summary
An interleaved encoder includes a number of encoders consisting of L parallel encoders, and a first switch circuit to sequentially couple an input node to an input port of one of the encoders. The input node receives a group of K*L symbols. Each symbol of the group of K*L symbols is received in synch with a respective clock pulse of a group of K*L clock pulses. The first switch circuit is synched with clock pulses of the group of K*L clock pulses, and sequentially couples the input node to an input port of a subsequent one of the encoders in response to each clock pulse of the group of K*L clock pulses.