Parallel FEC Interleaving for Low-Latency Data Transmission
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Solution Overview
Problem
Current data transmission methods in high-speed networks face challenges with bit error correction due to increased signal loss and intersymbol interference, particularly with the existing interleaving methods that introduce delays and reduce the effectiveness of FEC units.
Innovation Solution
Implementing a method that uses multiple FEC units to perform interleaving and de-interleaving, allowing data streams with channel identifiers to be sent and decoded separately, reducing the burden on individual FEC units and eliminating the need for row-writing and column-reading interleaving.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional row-writing and column-reading interleaving is used, then bit error correction capability is improved, but transmission delay increases and system complexity increases
Solution Approach 1:
The patent divides the data stream into multiple parallel sub-streams, each processed by separate FEC units. This segmentation allows simultaneous processing of multiple data portions without sequential interleaving operations, thereby maintaining error correction capability while reducing transmission delay.
Solution Approach 2:
The patent performs preliminary FEC encoding on multiple sub-streams before transmission, and the receiving end performs corresponding decoding operations. This preliminary action enables error correction to be prepared in advance without requiring post-transmission interleaving operations, reducing overall transmission delay.
2Reliability
If traditional row-writing and column-reading interleaving is used, then bit error correction capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the data processing into multiple parallel FEC units that independently encode and decode sub-streams. This eliminates the need for complex row-writing and column-reading interleaving logic, reducing device complexity while maintaining error correction capability through parallel processing.
Solution Approach 2:
The patent combines multiple FEC units to process different sub-streams simultaneously, merging their capabilities to achieve the error correction function that would otherwise require complex sequential interleaving operations, thereby simplifying the overall system architecture.
3Reliability
If multiple FEC units are used for parallel processing, then error correction capability is improved, but device complexity increases
Solution Approach 1:
The patent divides the data stream into multiple sub-streams that can be independently processed by separate FEC units. This segmentation enables parallel error correction processing, improving reliability while distributing the processing load across multiple simpler units rather than requiring one complex sequential processor.
Data Source
AI summary
An embodiment of the present disclosure contemplates a data sending and receiving method and apparatus. A first FEC unit of a sending device sends, by using a first channel, a first data stream on which first FEC encoding has been performed; a second FEC unit of the sending device sends, by using a second channel, a second data stream on which second FEC encoding has been performed; and the sending device performs interleaving on the first data stream and the second data stream, to obtain an output data stream, and sends the output data stream to a receiving device and error correction capability of a receiving device could be improved. In addition, in the present disclosure, an operation of writing by row and reading by column does not need to be performed. Therefore, no delay is generated.