Parallel FEC Interleaving for High-Speed Ethernet Error Correction

Solution Overview

Problem

Existing data transmission methods face challenges in efficiently correcting bit errors in high-speed Ethernet interfaces due to increased signal loss and intersymbol interference, which can lead to delayed data processing and reduced error correction capabilities.

Innovation Solution

A data sending method and device that utilize multiple forward error correction (FEC) units to encode and interleave data streams, allowing for de-interleaving and FEC decoding by different units in the receiving device, thereby reducing the burden on individual FEC units and improving error correction efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data is written by row and read by column through an interleaver, then error correction capability is improved by distributing bit errors across different code words, but transmission delay increases due to the need to write complete data sections before reading

Engineering Contradiction:

Improveerror correction capabilityVSAvoidtransmission delay

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent divides the data stream into multiple parallel lanes, with each lane processed by a separate FEC unit. This segmentation allows simultaneous processing of multiple data portions without requiring complete data buffering, thereby reducing transmission delay while maintaining error correction capability through distributed error handling across lanes.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent performs FEC encoding on data segments before they are fully assembled, allowing parallel processing of multiple data portions. By preparing error correction codes in advance for each lane independently, the system avoids waiting for complete data sections, thus reducing delay while maintaining reliability.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If multiple FEC units are used to process different data streams, then error correction capability is improved by distributing the correction burden, but device complexity increases

Engineering Contradiction:

Improveerror correction capabilityVSAvoidnumber of FEC units

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the data stream into multiple parallel lanes, with each lane processed by a separate FEC unit. This segmentation allows simultaneous processing of multiple data portions without requiring complete data buffering, thereby reducing transmission delay while maintaining error correction capability through distributed error handling across lanes.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent employs multiple FEC units that can process different data streams simultaneously, where each unit is designed with the same functional capabilities. This universality allows the system to handle multiple data lanes with identical processing logic, improving error correction capability while managing complexity through standardized, reusable processing modules.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If traditional interleaving is used to distribute bit errors, then error correction success rate is improved, but the system requires complex interleaving mechanisms that increase device complexity

Engineering Contradiction:

Improveerror correction success rateVSAvoidinterleaving mechanism complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the data stream into multiple parallel lanes, with each lane processed by a separate FEC unit. This segmentation allows simultaneous processing of multiple data portions without requiring complete data buffering, thereby reducing transmission delay while maintaining error correction capability through distributed error handling across lanes.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent performs FEC encoding on data segments before they are fully assembled, allowing parallel processing of multiple data portions. By preparing error correction codes in advance for each lane independently, the system avoids waiting for complete data sections, thus reducing delay while maintaining reliability.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12224858B2Data sending and receiving method and device

Publication Date: 2025.02.11 HUAWEI TECH CO LTD

AI summary

An embodiment of the present disclosure contemplates a data sending and receiving method and apparatus. A first FEC unit of a sending device sends, by using a first channel, a first data stream on which first FEC encoding has been performed; a second FEC unit of the sending device sends, by using a second channel, a second data stream on which second FEC encoding has been performed; and the sending device performs interleaving on the first data stream and the second data stream, to obtain an output data stream, and sends the output data stream to a receiving device.