Parallel FEC Encoding for Fixed-Latency Ethernet PHY Timing
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Solution Overview
Problem
Traditional Ethernet PHY transceivers experience variable latency and complexity in data transmission due to integrated FEC blocks, which complicates timestamping and compliance with TSN and IEEE 1588 standards.
Innovation Solution
Implementing a parallel FEC encoder and decoder in the transmit and receive data paths, respectively, to reduce latency and variability by operating on different symbol widths, using a single data width converter, and employing a latency predictor with a look-up table for fixed latency adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If integrated FEC blocks are used in traditional Ethernet PHY transceivers, then error correction capability is improved, but latency and variability increase
Solution Approach 1:
The patent segments the FEC processing into separate transmit and receive paths with parallel operation. The transmit path processes data at one symbol width while the receive path operates at a different symbol width, allowing independent optimization of each path to minimize latency while maintaining error correction capability.
Solution Approach 2:
The patent implements preliminary action by using a latency predictor with look-up table that pre-calculates and stores latency values for different data widths and FEC configurations. This allows the system to compensate for FEC-induced latency variations in advance, ensuring consistent timing behavior.
2Reliability
If integrated FEC blocks are used in traditional Ethernet PHY transceivers, then error correction capability is improved, but device complexity increases
Solution Approach 1:
The patent divides the complex FEC processing into separate, modular transmit and receive blocks that operate independently. This segmentation allows each block to be optimized separately and simplifies the overall system architecture by eliminating the need for complex integrated FEC blocks that handle both transmission and reception in a unified manner.
Solution Approach 2:
The patent transitions from a single-dimension integrated FEC block to a multi-dimensional parallel processing architecture where transmit and receive paths operate simultaneously at different symbol widths. This dimensional change allows the system to handle complexity through parallelism rather than sequential integration.
3Reliability
If integrated FEC blocks are used in traditional Ethernet PHY transceivers, then error correction capability is improved, but timestamping compliance with TSN and IEEE 1588 standards becomes difficult
Solution Approach 1:
The patent implements preliminary action through a latency predictor that pre-calculates latency values and stores them in a look-up table. This allows the system to compensate for timing variations introduced by FEC processing in advance, ensuring that timestamping operations can accurately reflect the true transmission timing and comply with TSN and IEEE 1588 standards.
Solution Approach 2:
The patent introduces an intermediary latency predictor component that mediates between the FEC processing blocks and the timestamping function. This intermediary calculates and provides latency compensation values that allow the timestamping mechanism to operate independently of FEC-induced timing variations, simplifying compliance with time-sensitive networking standards.
Data Source
AI summary
An apparatus comprises a data width converter and a forward error correction (FEC) encoder. The data width converter includes an input to receive an input data stream at an input bit width, a first output to produce a first output data stream at a first output bit width, and a second output to produce a second output data stream at a second output bit width. The FEC encoder includes an input to receive the second output data stream at the second output bit width. The FEC encoder includes an output to produce parity bits at least partially based on multiple received symbols of the second output data stream having the second output bit width. The parity bits for insertion in the first output data stream having the first output bit width. In one or more examples, the data width converter is in a transmit data path, and the FEC encoder is in parallel with the transmit data path.