Parallel FEC Encoding for Fixed-Latency Transmit Data Paths
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Solution Overview
Problem
Traditional Ethernet physical layer transceivers experience variable latency due to the integration of Forward Error Correction (FEC) blocks in the data path, leading to complex predictor logic and increased latency variability, which complicates time synchronization and compliance with standards like IEEE 1588 and TSN.
Innovation Solution
The proposed solution involves parallelizing the FEC encoder with the transmit data path, allowing the FEC encoder to operate independently and reducing the number of data width converters, thereby ensuring a fixed latency in the data conveyance and simplifying latency prediction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FEC blocks are integrated in the data path, then error correction capability is improved, but latency variability increases
Solution Approach 1:
The patent segments the FEC processing from the main data path by using a separate parallel processing path. The transmit data path and FEC encoder operate independently, with the FEC encoder receiving data through a separate interface. This segmentation eliminates the coupling between data transmission and error correction processing, thereby reducing latency variability while maintaining error correction capability.
2Reliability
If FEC blocks are integrated in the data path, then error correction capability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the FEC encoder from the integrated data path and places it in a separate parallel processing path. The FEC encoder is taken out of the critical data transmission path, eliminating the need for complex predictor logic to manage timing and latency. This extraction simplifies the overall device complexity while preserving the error correction function.
3Loss of time
If parallel FEC encoding is used, then latency is reduced, but data path structure becomes more complex
Solution Approach 1:
The patent merges the FEC encoding function with the existing data path infrastructure by using shared components such as the data width converter and interface logic. Although the FEC encoder operates in parallel, it utilizes shared resources and coordinated control mechanisms to minimize additional structural complexity. This merging approach achieves low latency through parallel processing while avoiding proportional increases in overall system complexity.
Data Source
AI summary
An apparatus comprises a data width converter and a forward error correction (FEC) encoder. The data width converter includes an input to receive an input data stream at an input bit width, a first output to produce a first output data stream at a first output bit width, and a second output to produce a second output data stream at a second output bit width. The FEC encoder includes an input to receive the second output data stream at the second output bit width. The FEC encoder includes an output to produce parity bits at least partially based on multiple received symbols of the second output data stream having the second output bit width. The parity bits for insertion in the first output data stream having the first output bit width. In one or more examples, the data width converter is in a transmit data path, and the FEC encoder is in parallel with the transmit data path.