Parallel FEC Receive Path for Fixed-Latency Ethernet PHYs
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Solution Overview
Problem
Traditional Ethernet PHY transceivers experience variable latency due to integrated FEC blocks and multiple data width converters, complicating timestamping and compliance with time-sensitive networking standards.
Innovation Solution
Implementing parallel FEC encoding and decoding in the transmit and receive data paths, with a single data width converter and a latency predictor using a look-up table to ensure fixed latency and reduce variability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If integrated FEC blocks are used in traditional Ethernet PHY transceivers, then error correction capability is improved, but latency variability increases
Solution Approach 1:
The patent segments the FEC processing into separate transmit and receive paths, with the transmit path handling encoding and the receive path handling decoding. This segmentation allows independent optimization of each path's latency characteristics and enables parallel processing operations.
Solution Approach 2:
The patent implements preliminary action by pre-calculating and storing latency values in a look-up table during the transmit path operation. The latency predictor uses these pre-computed values to compensate for FEC processing delays in the receive path, ensuring fixed latency without requiring real-time complex calculations.
2Adaptability or versatility
If multiple data width converters are used in traditional Ethernet PHY transceivers, then data rate adaptability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the data width conversion function from multiple separate converters and consolidates it into a single data width converter in the receive path. This single converter handles all data width transformations by working in conjunction with the parallel FEC decoding architecture, significantly reducing device complexity while maintaining data rate adaptability.
3Reliability
If integrated FEC blocks are used in traditional Ethernet PHY transceivers, then error correction is improved, but timestamping complexity increases
Solution Approach 1:
The patent introduces a latency predictor as an intermediary component that sits between the FEC decoding process and the timestamping function. This mediator translates the variable latency characteristics of FEC processing into fixed latency values using pre-computed look-up tables, thereby simplifying timestamping operations while preserving error correction capabilities.
4Loss of time
If parallel FEC decoding is implemented, then latency is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by pre-calculating all timing and latency compensation values during the manufacturing and initialization phase, storing them in look-up tables. This approach transfers the precision requirements from runtime operations to the initialization phase, allowing the parallel FEC decoding to operate with relaxed real-time timing constraints while maintaining high precision through pre-computed values.
Data Source
AI summary
An apparatus comprises a data width converter and a forward error correction (FEC) decoder. The data width converter includes an input to receive an input data stream having an input bit width, a first output to produce a first output data stream having a first output bit width, and a second output to produce a second output data stream having at least a second output bit width. The FEC decoder includes an input to receive the second output data stream having the at least second output bit width. The FEC decoder includes an error correction output to produce one or more error correction values at least partially based on one or more FEC code words in the second output data stream. The one or more error correction values are for correction of one or more symbols, one or more partial symbols, or both, in the first output data stream.