Parallel FEC Interleaving for Low-Delay Data Reception
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Solution Overview
Problem
Current data transmission methods in high-speed networks face challenges with bit error correction due to increased signal loss and intersymbol interference, particularly with the existing interleaving techniques that introduce delays and reduce the effectiveness of FEC units.
Innovation Solution
The proposed method involves using multiple FEC units and performing interleaving and de-interleaving to distribute bit errors across different FEC units, allowing for efficient error correction without the need for complex interleaving techniques like writing by row and reading by column, thereby reducing delay and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional row-writing column-reading interleaving is used, then bit error distribution is improved, but transmission delay increases significantly
Solution Approach 1:
The patent divides the data stream into multiple parallel lanes and processes them independently through multiple FEC units simultaneously. Instead of collecting all data into a single interleaved sequence, the system segments the processing across multiple channels, allowing parallel error correction without sequential delays.
Solution Approach 2:
The patent performs FEC encoding and lane distribution in advance before transmission, organizing data into parallel lanes that can be processed independently. This preliminary organization eliminates the need for complex post-reception interleaving operations, reducing processing delay while maintaining error correction effectiveness.
2Reliability
If complex interleaving techniques are used, then error correction effectiveness is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent segments the error correction function across multiple independent FEC units, each handling a specific lane. This segmentation replaces complex centralized interleaving logic with simpler distributed processing, reducing overall device complexity while maintaining or improving error correction effectiveness through parallel operation.
Solution Approach 2:
Each FEC unit is designed to handle multiple functions: encoding, lane identification, and error correction within its designated lane. This multi-functionality eliminates the need for separate interleaving and de-interleaving devices, reducing system complexity while achieving the same error correction goals.
3Reliability
If traditional interleaving methods are used, then bit errors are distributed across code words, but power consumption increases
Solution Approach 1:
The patent segments the error correction workload across multiple parallel FEC units operating simultaneously. This segmentation allows the system to achieve effective bit error distribution through parallel processing rather than sequential interleaving operations, significantly reducing the computational power and energy consumption required.
Solution Approach 2:
The patent establishes continuous parallel processing across multiple lanes, where each FEC unit continuously processes its assigned lane without interruption. This continuous parallel action eliminates the stop-start nature of traditional interleaving, maintaining constant error protection while reducing overall power consumption through efficient resource utilization.
Data Source
AI summary
An embodiment of the present invention discloses a data sending and receiving method. A first FEC unit of a sending device sends, by using a first channel, a first data stream on which first FEC encoding has been performed; a second FEC unit of the sending device sends, by using a second channel, a second data stream on which second FEC encoding has been performed; and the sending device performs interleaving on the first data stream and the second data stream, to obtain an output data stream, and sends the output data stream to a receiving device and error correction capability of a receiving device could be improved. In addition, in the present invention, an operation of writing by row and reading by column does not need to be performed. Therefore, no delay is generated.