Parallel FEC Interleaving for Low-Latency Data Reception

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Solution Overview

Problem

Current data transmission methods in high-speed networks face challenges with bit error correction due to increased signal loss and intersymbol interference, particularly with the existing interleaving methods that introduce delays and reduce the effectiveness of FEC units.

Innovation Solution

Implementing a method where multiple FEC units perform interleaving and de-interleaving on data streams, allowing error correction to be distributed across different units, reducing the burden on individual FEC units and eliminating the need for complex row-column interleaving, thereby reducing power consumption and avoiding transmission delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If row-column interleaving is used to distribute bit errors across FEC units, then error correction capability is improved, but transmission delay increases due to the need to write complete sections before reading

Engineering Contradiction:
Improveerror correction capabilityVSAvoidtransmission delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent divides the data stream into multiple parallel channels, each processed by a separate FEC unit. Instead of using complex row-column interleaving that requires buffering entire sections, the system segments the data flow so that each FEC unit independently handles its assigned channel, eliminating the need to wait for complete section writing before reading can begin.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary distribution of data to multiple FEC units before transmission, allowing each unit to process its assigned data independently and simultaneously. This preliminary segmentation and distribution eliminates the need for post-transmission row-column reordering, thereby avoiding the transmission delays that would otherwise be required to complete the interleaving process.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If row-column interleaving is implemented, then bit error distribution across code words is improved, but device complexity increases

Engineering Contradiction:
Improvebit error distributionVSAvoidinterleaving complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent simplifies the interleaving process by segmenting the data stream into multiple independent channels that are processed in parallel. Each channel is handled by a separate FEC unit without requiring complex row-column reordering logic, thereby reducing device complexity while still achieving effective bit error distribution across multiple code words.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent combines multiple simple FEC units processing independent channels to achieve the same error correction效果 as a single complex row-column interleaving system. By merging multiple simple processing paths rather than using one complex sequential process, the system reduces overall device complexity while maintaining or improving bit error distribution.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If multiple FEC units are used to process data streams, then error correction effectiveness is improved, but power consumption increases

Engineering Contradiction:
Improveerror correction effectivenessVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent segments the data processing task across multiple FEC units operating in parallel, where each unit handles a specific channel independently. This segmentation allows for more efficient power utilization compared to sequential row-column interleaving, as multiple units can process data simultaneously without the need for complex buffering and reordering operations that consume additional power.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent enables continuous processing of data streams across multiple FEC units without interruption for interleaving operations. Each FEC unit continuously processes its assigned channel in real-time, eliminating the idle periods and redundant operations associated with row-column interleaving, thereby improving error correction effectiveness while reducing overall power consumption.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS10797828B2Data receiving method and device, and data sending method and device
Publication Date: 2020.10.06 HUAWEI TECH CO LTD
  • US10797828B2 patent drawing
  • US10797828B2 patent drawing
  • US10797828B2 patent drawing

AI summary

An embodiment of the present invention discloses a data sending and receiving method. A first FEC unit of a sending device sends, by using a first channel, a first data stream on which first FEC encoding has been performed; a second FEC unit of the sending device sends, by using a second channel, a second data stream on which second FEC encoding has been performed; and the sending device performs interleaving on the first data stream and the second data stream, to obtain an output data stream, and sends the output data stream to a receiving device and error correction capability of a receiving device could be improved. In addition, in the present invention, an operation of writing by row and reading by column does not need to be performed. Therefore, no delay is generated.