Parallel FEC Interleaving for 1 Tbps Optical Transmission
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Solution Overview
Problem
High-speed optical transmission systems face challenges in supporting 1 Tbps-class transmission capacity due to the difficulty of performing error correction coding in a single circuit, which requires large-capacity memories for interleaving and deinterleaving, leading to increased process delay and circuit size.
Innovation Solution
A transmission device employing concatenated error correction codes with an outer code interleaver, outer and inner coding units, and interleavers/deinterleavers to distribute and restore bit sequences, eliminating the need for memory-based interleaving and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory-based interleaving is used for error correction coding, then burst error correction capability is improved, but circuit size and process delay increase
Solution Approach 1:
The patent divides the interleaving function into multiple parallel interleavers that process different segments of the bit sequence simultaneously. Each interleaver handles a portion of the data with reduced memory requirements, while the collective system maintains the burst error correction capability of the original single large interleaver.
Solution Approach 2:
The patent transitions from time-based sequential interleaving to a spatial parallel architecture where multiple interleavers operate concurrently. This dimensional change from temporal to spatial processing reduces the memory depth required in each individual interleaver while maintaining overall interleaving effectiveness.
2Reliability
If memory-based interleaving is used for error correction coding, then burst error correction capability is improved, but process delay increases
Solution Approach 1:
The patent segments the interleaving process into multiple parallel paths, each handling a subset of the data. This segmentation allows simultaneous processing of multiple data streams, reducing the overall process delay while maintaining the burst error correction capability through coordinated output from all interleavers.
Solution Approach 2:
The patent implements continuous parallel processing where multiple interleavers operate simultaneously without sequential waiting. This continuity eliminates the time delays associated with sequential memory access and processing, maintaining high throughput while providing effective burst error correction.
3Device complexity
If single-circuit error correction coding is used, then coding simplicity is maintained, but transmission capacity for 1 Tbps-class systems cannot be supported
Solution Approach 1:
The patent divides the error correction coding function into multiple parallel coding circuits, each handling a portion of the transmission data. This segmentation enables the system to achieve 1 Tbps-class transmission capacity through parallel processing while keeping each individual circuit relatively simple and manageable.
Solution Approach 2:
The patent designs the parallel coding circuits to use standardized, reusable components that can be replicated and configured for different capacity requirements. This universality allows the system to scale from lower to higher transmission capacities by simply adding or removing identical circuit modules, maintaining design simplicity while achieving high productivity.
Data Source
AI summary
A transmission device includes an outer code interleaver that generates multiple bit sequences while performing interleaving on a signal formed of multiple multilevel modulation symbols on a per-bit basis, an outer coding unit that performs outer coding processings, in parallel, on the multiple respective bit sequences generated by the interleaving, an outer code deinterleaver that performs deinterleaving on bit sequences obtained by performing the outer coding processings, the deinterleaving being inverse operation of the interleaving performed by the outer code interleaver, an inner coding unit that performs inner coding processings, in parallel, on bit sequences obtained by performing the deinterleaving in the outer code deinterleaver, and an inner code interleaver that performs time interleaving and symbol interleaving on bit sequences obtained by performing the inner coding processings.