Parallel FEC Receive Path for Fixed-Latency Ethernet PHYs

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Traditional Ethernet PHY transceivers experience variable latency due to integrated Forward Error Correction (FEC) blocks and multiple data width converters, complicating timestamping and compliance with time-sensitive networking standards.

Innovation Solution

Implementing parallel FEC encoding and decoding processes in the transmit and receive data paths, reducing latency and latency variation by using a single data width converter and a latency predictor, such as a look-up table, to ensure fixed latency and accurate timestamping.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If integrated FEC blocks are used in traditional Ethernet PHY transceivers, then error correction capability is improved, but latency and latency variation increase

Engineering Contradiction:

Improveerror correction capabilityVSAvoidlatency and latency variation

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The FEC decoding process is segmented into parallel operations: syndrome calculation, error location determination, and error correction. Multiple syndromes are calculated in parallel for different powers of the generator polynomial, enabling simultaneous error detection and correction without sequential processing delays.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system pre-calculates and stores syndrome values in lookup tables before actual data reception. When errors occur, the pre-computed syndromes are immediately retrieved and applied, eliminating the need for real-time complex polynomial calculations and reducing decoding latency.

Inventive Principle:

Principle #10Preliminary action

2Adaptability or versatility

If multiple data width converters are used in traditional Ethernet PHY transceivers, then data rate adaptation is improved, but device complexity and latency increase

Engineering Contradiction:

Improvedata rate adaptationVSAvoidnumber of data width converters

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

Multiple data width conversion functions are merged into a single converter. The converter simultaneously handles different data widths (64-bit, 70-bit, 80-bit) and FEC encoding/decoding operations through a unified architecture, eliminating the need for separate converters for each function and reducing overall system complexity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The data width converter is designed with universal functionality to perform multiple operations: data width conversion, FEC encoding, and FEC decoding. By making the converter multi-functional, the system reduces the total number of components while maintaining adaptability to different data rates and protocols.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Productivity

If multiple data width converters and integrated FEC blocks are used, then data processing capability is improved, but timestamping accuracy and TSN compliance become difficult to achieve

Engineering Contradiction:

Improvedata processing capabilityVSAvoidtimestamping accuracy

Core Design Contradiction:

ProductivityVSMeasurement precision

Solution Approach 1:

The FEC decoding operation is extracted from the main data path and performed in parallel. This separation allows the critical data path to maintain fixed, predictable latency while FEC processing occurs independently, enabling accurate timestamping and compliance with Time-Sensitive Networking requirements.

Inventive Principle:

Principle #2Taking out (Extraction)

4Adaptability or versatility

If variable latency is present in the PHY transceiver, then flexibility in processing is improved, but compliance with IEEE 1588 and TSN standards deteriorates

Engineering Contradiction:

Improveprocessing flexibilityVSAvoidcompliance with IEEE 1588 and TSN standards

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The system dynamically selects between different operating modes (different data widths and FEC configurations) while maintaining fixed latency characteristics in each mode. The latency predictor adaptively adjusts to different operational states without introducing variable latency, ensuring both flexibility and compliance with timing-critical standards.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS12395188B2Apparatus and method for processing receive data in a receive data path including parallel FEC decoding

Publication Date: 2025.08.19 MICROCHIP TECHNOLOGY INC

AI summary

An apparatus comprises a data width converter and a forward error correction (FEC) decoder. The data width converter includes an input to receive an input data stream having an input bit width, a first output to produce a first output data stream having a first output bit width, and a second output to produce a second output data stream having at least a second output bit width. The FEC decoder includes an input to receive the second output data stream having the at least second output bit width. The FEC decoder includes an error correction output to produce one or more error correction values at least partially based on one or more FEC code words in the second output data stream. The one or more error correction values are for correction of one or more symbols, one or more partial symbols, or both, in the first output data stream.