Parallel FET Driver Circuit With Adaptive Power Stage Partitioning

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Solution Overview

Problem

Existing power stage partitioning solutions in electronic converters struggle to dynamically adapt to changing operating conditions, such as supply voltage, switching frequency, and temperature, leading to suboptimal efficiency due to fixed current thresholds.

Innovation Solution

A driver circuit that dynamically adjusts current thresholds based on real-time operating conditions by using a current sensor, reference capacitance, resistance, and control circuits to generate adaptive drive signals for FETs, allowing for dynamic partitioning of the power stage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If fixed current thresholds are used for power stage partitioning, then device complexity is reduced, but adaptability to changing operating conditions deteriorates

Engineering Contradiction:
Improvecontrol circuit complexityVSAvoidadaptability to operating conditions
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic current thresholds that automatically adjust based on real-time operating conditions such as supply voltage, temperature, and load current. The control circuit continuously monitors these parameters and modifies the current thresholds accordingly, transforming a static system into a dynamic one that adapts to changing conditions without increasing overall system complexity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent employs feedback mechanisms where the control circuit monitors operating conditions (supply voltage, temperature, load current) and uses this information to adjust the current thresholds for power stage partitioning. This closed-loop feedback ensures the system automatically optimizes its performance based on actual operating conditions rather than relying on fixed predetermined values.

Inventive Principle:
Principle #23Feedback

2Reliability

If the number of active FETs is increased, then switch-on resistance is reduced, but switching losses increase

Engineering Contradiction:
Improveconduction performanceVSAvoidswitching losses
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent dynamically adjusts the number of active FETs in each parallel group based on real-time operating conditions. The control circuit monitors parameters such as supply voltage, temperature, and load current to determine the optimal partitioning configuration, allowing the system to transition between different numbers of active FETs as conditions change, thereby optimizing the trade-off between conduction performance and switching losses.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the operational parameters of the power stage by adjusting which specific FET groups are activated based on operating conditions. Different groups of FETs may have different characteristics, and the control circuit selects and activates appropriate groups by changing the effective parameters of the power stage configuration to match current operating requirements.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250023449A1Driver circuit comprising a power stage, related half-bridge driver circuit, control circuit for an electronic converter, integrated circuit and method
Publication Date: 2025.01.16 STMICROELECTRONICS SRL
  • US20250023449A1 patent drawing
  • US20250023449A1 patent drawing
  • US20250023449A1 patent drawing

AI summary

A power stage includes parallel FETs including a reference FET. An input PWM signal has a switching period. A current sensor senses current flowing through the power stage during switch-on period. A first circuit generates a first PWM signal having a duty-cycle indicative of reference FET driving losses for a reference current. A second circuit generates a second PWM signal having a duty-cycle indicative of reference FET conduction losses for that reference current. The duty cycles of the first and second PWM signals are compared to generate a comparison signal. The reference current is changed until a logic state of the comparison signal changes. A respective enable signal for each FET is generated by comparing the reference current to the sensed current flowing through the power stage. A FET driver circuit generates a respective drive signal for each FET by combining the respective enable signal with the input PWM signal.