Parallel FET Stack RF Switches for Faster TX/RX Settling
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Solution Overview
Problem
Conventional RF switches with large FET stacks experience slow settling times when switching between transmit and receive states, limiting system performance and data throughput.
Innovation Solution
Implementing RF switches with multiple FET stacks arranged in parallel between switch ports, which reduces the power handling requirement for each stack, allowing for smaller FETs with lower gate capacitance and faster switching times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If large FET stacks are used in RF switches to achieve higher power handling capability, then power handling capability is improved, but settling time increases and becomes relatively slow
Solution Approach 1:
The patent divides a single large FET stack into multiple smaller FET stacks connected in parallel. Each smaller stack handles a portion of the total power, reducing the power burden on individual transistors. This segmentation allows each FET to have smaller gate capacitance while collectively maintaining the required power handling capability, thereby reducing the settling time without sacrificing power handling capability.
2Power
If larger FETs are used to handle higher power, then power handling capability is improved, but gate capacitance increases leading to slower switching
Solution Approach 1:
The patent segments the power handling function across multiple parallel FET stacks. Each FET in the parallel configuration handles a fraction of the total power, allowing the use of smaller transistors with lower gate capacitance. This enables faster switching speeds while collectively maintaining the required power handling capability through the parallel arrangement.
Solution Approach 2:
The patent combines multiple parallel FET stacks to achieve the required power handling capability. By merging the current handling capacity of several smaller FETs in parallel, the system achieves equivalent or superior power handling to a single large FET while benefiting from the faster switching characteristics of smaller devices with lower gate capacitance.
Data Source
AI summary
A switch circuit includes first and second transistor stacks coupled in parallel between first and second ports. The first transistor stack includes a first plurality of transistors coupled in series between the first and second ports to provide a first variably-conductive path between the first and second ports. Each transistor of the first plurality of transistors has a gate terminal coupled to a first control terminal. The second transistor stack includes a second plurality of transistors coupled in series between the first and second ports to provide a second variably-conductive path between the first and second ports. Each transistor of the second plurality of transistors has a gate terminal coupled to a second control terminal. When implemented in a transceiver, first and second drivers are configured to simultaneously configure the first and second variably-conductive paths in a low-impedance state.