Parallel FET Circuit With Sensor-Gated Stages for Lower Switching Loss
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Field-effect transistors in power electronics experience significant energy losses due to large gate capacitances and frequent switching cycles, which are particularly problematic in battery-powered electric vehicles where energy efficiency is critical.
Innovation Solution
A circuit design incorporating multiple transistors with adjustable threshold voltages and resistors to distribute current based on demand, reducing the number of transistors used during low-demand phases and minimizing gate capacitance charging, thereby optimizing energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate circuits are used for controlling different transistor groups, then control precision is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple control functions into a single control circuit that can selectively control different transistor groups (first, second, and third transistor groups) through a unified control signal mechanism. The control circuit integrates the functions that would otherwise require separate circuits, thereby reducing device complexity while maintaining the precision of controlling different transistor groups independently when needed.
2Loss of energy
If transistor size is increased to reduce switching losses, then power efficiency is improved, but device area increases
Solution Approach 1:
The patent divides the transistor structure into multiple groups (first transistor group, second transistor group, third transistor group) with different size characteristics. The first transistor group has a first channel width, the second transistor group has a second channel width, and the third transistor group has a third channel width. This segmentation allows smaller individual transistors to be used while reducing switching losses, avoiding the need for a single large transistor that would increase device area.
Solution Approach 2:
Different transistor groups are assigned different channel widths based on their specific functional requirements. The first transistor group operates with a first channel width optimized for its function, the second transistor group with a second channel width, and the third transistor group with a third channel width. This local optimization allows each transistor group to achieve efficient switching with appropriately sized transistors, reducing overall device area while maintaining power efficiency.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
The present invention relates to a circuit (1) intended to be combined in series with a load to be supplied (3), comprising: a first field effect transistor (100); at least one second field effect transistor (102) combined in parallel with the first transistor; and at least one sensor (130) for information representative of a current transmitted to said load, the gate of the second transistor being connected to an output (150) of said sensor.