Parallel Power FET Timing Synchronization for Even Current Sharing
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Solution Overview
Problem
The uneven distribution of current flow among power FETs connected in parallel due to differing RDS(on) and threshold voltage mismatches leads to unequal FET temperatures and potential damage.
Innovation Solution
A circuit with integrated circuits and a control circuit (synchronizer) synchronizes the turn-on and turn-off times of parallel FETs using phase detectors to adjust their timing based on compared phase output signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If power FETs are connected in parallel to handle high current applications, then the current handling capability is improved, but uneven current distribution occurs due to differing RDS(on) and threshold voltage mismatches
Solution Approach 1:
The patent introduces individual delay adjustment mechanisms for each parallel FET driver circuit, allowing localized timing compensation. Each FET receives a customized gate drive signal with adjusted delay time based on its specific threshold voltage and RDS(on) characteristics, thereby achieving uniform current distribution while maintaining high current handling capability
Solution Approach 2:
The patent modifies the timing parameters of gate drive signals by introducing adjustable delay circuits. By changing the delay time parameter for each FET driver, the turn-on and turn-off moments are synchronized across parallel FETs, compensating for manufacturing variations in threshold voltage and RDS(on) without altering the FETs themselves
2Object-affected harmful factors
If driver turn-on is slowed to minimize EMI, then electromagnetic interference is reduced, but FET turn-on time differences increase due to driver delay variations
Solution Approach 1:
The patent implements preliminary delay adjustment for each driver circuit before the actual switching operation. By pre-configuring appropriate delay times in each driver based on the specific FET characteristics, the system achieves synchronized turn-on while maintaining slowed rise rates to minimize EMI
Solution Approach 2:
The patent introduces dynamically adjustable delay parameters in each driver circuit, allowing the turn-on timing to be optimized for each specific FET. This dynamic adjustment capability enables simultaneous achievement of EMI reduction through controlled rise rates and turn-on time synchronization through individualized delay settings
3Device complexity
If no synchronization circuit is used, then device complexity is reduced, but FET temperature differences and potential damage occur due to unequal current distribution
Solution Approach 1:
The patent employs feedback mechanisms where the actual turn-on and turn-off times of parallel FETs are monitored and compared. Based on this feedback, the delay adjustment circuits are dynamically tuned to achieve synchronized switching, ensuring uniform current distribution and preventing thermal runaway while maintaining manageable circuit complexity
Solution Approach 2:
The patent replaces complex mechanical or hardware-based synchronization mechanisms with electronic delay adjustment circuits implemented through standard semiconductor components. This substitution achieves reliable FET synchronization and temperature均衡 with significantly reduced circuit complexity compared to traditional mechanical synchronization approaches
Data Source
AI summary
A circuit for synchronizing the turn-on/turn-off times of parallel FETs. The circuit includes a plurality of integrated circuits and a synchronizer. Each of the integrated circuits includes a power FET which operates in parallel with the power FETs of the other integrated circuits, and a phase detector. The phase detector receives and compares the phase output signal of the integrated circuit with the phase output signal of another integrated circuit, and provides signals to the synchronizer regarding the relative turn-on times of the power FETs based upon the phase output signals. The synchronizer, in response to the signals from each of the integrated circuits, reduces or increases the turn-on times of the power FETs, thereby synchronizing the turn-on times of the power FETs.