Parallel FFT IP Core Architecture for FPGA Time Delay Reduction
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Solution Overview
Problem
Conventional Fast Fourier Transform (FFT) intellectual property (IP) cores on Field Programmable Gate Arrays (FPGAs) cause long time delays, which hinder performance in high-speed systems, such as high-speed communication systems, by covering calculated data during iterative parameter estimation.
Innovation Solution
The method involves decomposing the FFT into four submodules and processing four parallel data channels in a deep pipeline architecture using an FFT decomposition module, a twiddle factor storage module, and an arithmetic operation processing module, reducing time delay by utilizing pre-stored twiddle factor data and parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional FFT IP core is used on FPGA, then the system structure is simple, but the time delay is long which causes calculated data to be covered
Solution Approach 1:
The patent divides the conventional single FFT IP core into four parallel N/4-point FFT sub-cores. Each sub-core processes a quarter of the input data independently, reducing the computational burden on each core and enabling parallel execution. This segmentation directly addresses the time delay issue by distributing the workload across multiple units that operate simultaneously.
Solution Approach 2:
The patent introduces a fourth dimension of parallel processing by implementing four separate FFT processing channels that operate concurrently. Instead of sequentially processing data through a single FFT core, the system processes four data streams in parallel, effectively adding a processing dimension that reduces overall computation time and eliminates the time delay problem.
2Productivity
If parallel processing is implemented to reduce time delay, then the processing speed increases, but the device complexity increases
Solution Approach 1:
The patent merges four separate N/4-point FFT processing results through a unified combination module that performs the final synthesis to produce the complete N-point FFT output. This merging approach allows parallel processing to achieve high productivity while consolidating the complexity into a dedicated combination module rather than distributing it throughout the entire system.
Solution Approach 2:
The patent implements preliminary decomposition of the input sequence into four subsequences before parallel FFT processing, and preliminary storage of twiddle factors in memory modules. These preliminary actions prepare the data and computational parameters in advance, enabling the parallel processing stages to operate efficiently without introducing additional complexity during the critical computation phase.
Data Source
AI summary
A method for accelerating fast Fourier transform (FFT) based on field programmable gate array is provided. A sequence requiring N-point FFT is decomposed equally into 4 subsequences. The 4 subsequences are processed through 4 parallel FFT intellectual property (IP) cores. Finally, an arithmetic operation is performed on the processed data and twiddle factor data pre-stored in a memory to obtain a result of the N-point FFT of an original sequence. An FFT decomposition module, a twiddle factor storage module, and an operation processing module are provided. Through the processing method, a time delay consumed by an N-point FFT operation can be reduced, and excellent application value can be achieved in a high-speed digital signal processing system.