Parallel FIFO Memory Circuits with Asymmetric Ports
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional first-in first-out (FIFO) memory circuits face issues with unacceptably long write-to-read latency, variability in latency for parameterizable applications, and data bottlenecks due to asynchronous and unpredictable clock frequencies, making them unsuitable for certain applications.
Innovation Solution
The solution involves concatenating multiple FIFOs in parallel with asymmetric input and output ports, utilizing a deserializer on the write interface and a serializer on the read interface to minimize write-to-read latency, and ensuring that at most two FIFOs are active at any given time to reduce power consumption and stabilize latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple FIFOs are concatenated in series to increase depth, then the overall depth of the memory circuit is improved, but the write-to-read latency becomes unacceptably long
Solution Approach 1:
The patent divides the deep FIFO into multiple shallower FIFOs connected in parallel rather than series. Each FIFO is assigned a specific depth (e.g., 512 words), and multiple instances are used simultaneously to achieve the desired total depth (e.g., 4096 words). This segmentation allows data to be written to and read from different FIFOs at the same time, dramatically reducing write-to-read latency compared to a single deep FIFO or series-connected FIFOs.
Solution Approach 2:
The patent transitions from a single-dimensional depth approach (one deep FIFO) to a multi-dimensional approach using multiple parallel FIFOs with different depth characteristics. By distributing data across multiple FIFOs in parallel, the system achieves both increased depth and reduced latency through dimensional diversification of the memory architecture.
2Adaptability or versatility
If FIFOs are operated in different clock domains to handle asynchronous read/write rates, then the adaptability to different clock frequencies is improved, but data bottlenecks occur causing unpredictable status flag behavior
Solution Approach 1:
The patent introduces a control logic unit that acts as an intermediary between the write and read operations. This control logic manages the operation of multiple FIFOs across different clock domains, coordinating write enable signals and read requests to ensure predictable status flag behavior. The control logic monitors FIFO depths and coordinates access patterns to prevent data bottlenecks even when operating in asynchronous clock domains.
Solution Approach 2:
The system implements feedback mechanisms where status flags from individual FIFOs are monitored and fed back to the control logic. This feedback allows the control logic to adjust write enable signals and read operations dynamically, ensuring that status flag behavior remains predictable even when multiple FIFOs operate in different clock domains with varying frequencies.
3Productivity
If all FIFOs are kept active to maximize data throughput, then the productivity is improved, but the power consumption increases significantly
Solution Approach 1:
The patent implements dynamic operation of FIFOs where not all FIFOs need to be active simultaneously. The control logic dynamically enables or disables specific FIFOs based on current write and read operations. When data is being written to one FIFO and read from another, other FIFOs can be placed in a low-power state. This dynamic activation reduces overall power consumption while maintaining high data throughput capability when needed.
Solution Approach 2:
The system uses periodic action patterns where FIFOs are activated in alternating cycles rather than continuously. The control logic coordinates periodic write operations to specific FIFOs and periodic read operations from different FIFOs, allowing inactive FIFOs to enter low-power states between cycles. This periodic activation maintains data throughput while significantly reducing average power consumption compared to continuous operation of all FIFOs.
Data Source
AI summary
Memory circuits that concatenate multiple FIFOs in parallel to increase the overall depth of the memory circuits. Asymmetric input and output ports can be provided by including a deserializer on the write interface of the memory circuit and/or a serializer on the read interface of the memory circuit. The deserializer disperses the data evenly across all FIFOs, minimizing the write-to-read latency. In some embodiments, at most two of the FIFOs are active at any given time, one being written and one being read, which reduces the overall power consumption of the memory circuit compared to known structures.