Parallel FinFETs with Distinct Crystal Orientations via Layer Bonding
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Solution Overview
Problem
Conventional FinFET fabrication methods result in sub-optimal performance due to the need for non-parallel fins in CMOS pairs with different channel crystal orientations, which is problematic in high-density circuit layouts and challenging for lithography.
Innovation Solution
A process involving bonding a first silicon layer with a specific crystalline orientation to a second silicon layer with a different orientation, followed by selective etching to form parallel fins with distinct crystal orientations for p-FinFETs and n-FinFETs, allowing both types of FinFETs to be aligned with different crystalline planes while being physically parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional FinFET fabrication methods are used to achieve different channel crystal orientations for p-FinFETs and n-FinFETs, then device performance is improved, but fins become non-parallel making lithography challenging and layout density reduced
Solution Approach 1:
The patent introduces a vertical dimension by stacking silicon layers with different crystal orientations. The first silicon layer has a first crystal orientation and the second silicon layer has a second crystal orientation different from the first. By etching through these stacked layers, parallel fins are formed that extend through multiple dimensions, allowing different channel orientations in the horizontal plane while maintaining parallel fin structures vertically.
Solution Approach 2:
The invention segments the silicon substrate into multiple stacked layers, each with distinct crystal orientations. The first silicon layer is segmented to form fins with a first crystal orientation, while the second silicon layer is segmented to form fins with a second crystal orientation. This segmentation allows independent optimization of each layer's crystal orientation for specific device types while maintaining overall fin parallelism.
2Reliability
If fins are made non-parallel to achieve different crystal orientations, then channel performance is optimized, but layout density and circuit integration are reduced
Solution Approach 1:
The patent resolves the layout density issue by moving the orientation differentiation to the vertical dimension through layered stacking. In the horizontal plane, fins from different silicon layers are positioned to be parallel, maximizing layout density. In the vertical dimension, the different crystal orientations of stacked layers provide the channel performance optimization, effectively separating the two requirements into different spatial dimensions.
3Ease of manufacture
If parallel fins are formed with the same crystal orientation, then lithography and layout are simplified, but device performance becomes sub-optimal
Solution Approach 1:
The invention creates a composite structure by bonding together silicon layers with different crystal orientations. This composite multi-layer silicon structure allows the formation of parallel fins that exhibit different crystallographic properties in different vertical layers, enabling both manufacturing simplicity and performance optimization to coexist in the composite structure.
Solution Approach 2:
The patent applies local quality by assigning different crystal orientations to specific vertical regions (silicon layers) based on device type requirements. The first silicon layer is configured with a crystal orientation optimized for p-FinFETs, while the second silicon layer is configured with a crystal orientation optimized for n-FinFETs. This local differentiation within the parallel fin structure achieves performance optimization without compromising manufacturing ease.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of CMOS FinFET pairs with improved performance by aligning n-FinFETs with (100) and p-FinFETs with (110) crystalline planes while maintaining parallel fin configurations, addressing lithography and layout constraints.
Implementation Method 1
A bonding processor is configured to bond a first silicon layer having a first crystalline orientation to a second silicon layer having a second crystalline orientation that is different from the first crystalline orientation
Implementation Method 2
A material growth processor is configured to form, in a region of a surface of the first silicon layer, a volume of material extending through the first silicon layer from the second layer up to the surface of first layer. The material has a crystalline orientation that substantially matches the crystalline orientation of second layer
Implementation Method 3
An etching processor is configured to selectively etch areas of the surface of the first layer that are outside of the region to create a first plurality of fins and areas inside the region to create a second plurality of fins. The first and second plurality of fins are parallel to each other
Data Source
AI summary
An integrated circuit includes at least one single-crystal fin having a first crystal orientation. The integrated circuit also includes at least one single-crystal fin having a second crystal orientation. The single-crystal fin having the first crystal orientation and the single-crystal fin having the second crystal orientation are substantially parallel.