Parallel Finite Field Multiplication via Cascaded Logic Modules
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Solution Overview
Problem
Existing finite field multiplication methods require polynomial multiplication and storage space, which are complex and inefficient, especially when the length of the finite field changes.
Innovation Solution
A parallel finite field multiplication device comprising M cascaded logic processing modules, each with four input ends and two output ends, performs multiplication without polynomial multiplication by using a shifter, XOR gates, and selectors to process operands step-by-step, allowing for finite field multiplication of different lengths without storage space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the look-up table method is used, then multiplication results can be obtained quickly, but storage space requirements increase significantly
Solution Approach 1:
The finite field multiplication process is segmented into M cascaded logic processing modules, where each module handles one bit of the multiplier. This segmentation eliminates the need for large lookup tables while maintaining parallel processing capability, as each module independently processes a portion of the multiplication using shift and XOR operations.
Solution Approach 2:
The patent replaces the mechanical lookup table storage system with a logical processing system using shift registers and XOR gates. Instead of storing all possible multiplication results in ROM, the system dynamically computes results through bitwise operations, substituting physical storage with computational logic.
2Ease of manufacture
If polynomial multiplication method is used, then finite field multiplication can be performed, but device complexity increases
Solution Approach 1:
The patent extracts only the essential operations needed for finite field multiplication - shift and XOR - while eliminating the complex polynomial multiplication process. By taking out just the necessary computational steps and implementing them through simple logic modules, the device achieves the same mathematical result with much lower complexity.
Solution Approach 2:
The patent changes the operational parameters from polynomial arithmetic to bitwise operations. Instead of performing complex polynomial multiplication and reduction, the system uses shift amounts and XOR operations with primitive polynomial coefficients, transforming the computational approach to achieve the same result more efficiently.
3Adaptability or versatility
If fixed-length finite field multiplication is implemented, then device structure is simplified, but adaptability to different field lengths decreases
Solution Approach 1:
The cascaded logic processing module structure provides universality by enabling the same device to handle finite field multiplication of different lengths. By adjusting the number of cascaded modules M and the shift amounts, the system can adapt to various field lengths without requiring structural reconfiguration, making the device multi-functional.
Solution Approach 2:
The patent introduces dynamic parameters including the number of cascaded modules M and the shift amounts that can be adjusted according to the required field length. This dynamic configuration allows the device to adapt to different multiplication lengths while maintaining the same basic structure, eliminating the need for fixed-length design.
Data Source
AI summary
A parallel finite field multiplication device is disclosed. The device comprises M cascaded logic processing modules, each of which comprises four input ends and two output ends for carrying out different finite multiplication in different length. The device is calculated step by step through M cascaded logic processing modules according to the number of cascaded logic processing modules. In this device, M cascaded logic processing modules may be used, according to different numbers of the cascaded logic processing modules, in finite field multiplication of different lengths, without needing to carry out polynomial multiplication.