Parallel Firmware Sequencing for Faster Memory Subsystem Power-Up

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Solution Overview

Problem

Conventional memory sub-systems experience prolonged power-up times due to sequential initialization of firmware components, leading to delays in handling non-I/O requests and violating service level agreements.

Innovation Solution

Parallel initialization of front-end, security, and back-end components in the firmware data path, with the front-end notifying the host of availability before the back-end completes initialization, and the back-end queuing requests during initialization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If sequential initialization of firmware components is used, then system stability is ensured, but power-up time is prolonged

Engineering Contradiction:
Improvesystem stabilityVSAvoidpower-up time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The front-end component performs initialization actions and notifies the host of availability before the back-end component completes its initialization. This preliminary action allows the host to begin receiving and queuing requests earlier, reducing overall power-up time while maintaining system stability through proper request queuing mechanisms.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The firmware initialization process is segmented into independent front-end and back-end components that can initialize in parallel. The front-end component (handling non-I/O requests) and back-end component (handling I/O requests) are divided as separate initialization units, allowing simultaneous execution without compromising system stability.

Inventive Principle:
Principle #1Segmentation

2Loss of time

If parallel initialization of firmware components is used, then power-up time is reduced, but system complexity increases

Engineering Contradiction:
Improvepower-up timeVSAvoidfirmware sequencing complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

A request queuing mechanism acts as an intermediary between the front-end and back-end components. The queue manages requests asynchronously, allowing parallel initialization while simplifying the coordination complexity. The queue absorbs the asynchrony between components, reducing the need for complex synchronization logic.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The front-end component provides feedback to the host about its availability status before back-end initialization completes. This feedback mechanism allows the host to adjust its request timing and understand system readiness states, reducing the complexity of managing parallel initialization sequences.

Inventive Principle:
Principle #23Feedback

3Productivity

If front-end notifies host of availability before back-end completes initialization, then service level agreements are met, but request handling complexity increases

Engineering Contradiction:
Improverequest handling speedVSAvoidrequest queuing complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system transitions from a single-dimensional sequential request handling model to a two-dimensional model where requests can be queued and processed asynchronously. The queue adds a temporal dimension, allowing requests to be accepted, stored, and processed later when the back-end is ready, thereby meeting service level agreements without proportionally increasing handling complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12379860B2Firmware power up sequencing in memory sub-systems
Publication Date: 2025.08.05 MICRON TECHNOLOGY INC
  • US12379860B2 patent drawing
  • US12379860B2 patent drawing
  • US12379860B2 patent drawing

AI summary

A front-end firmware component of a memory sub-system receives a first request to perform a first set of initialization operations and initiates a first set of initialization operations for the front-end component in parallel with initiating a second set of initialization operations for a back-end component. Responsive to completing the first set of initialization operations, the front-end component sends a first notification to a host computer system to indicate that the front-end component is available to respond to requests for configuration data associated with the memory sub-system, receives a second request from the host computer system for a configuration data associated with the memory sub-system, and responsive to receiving the second request from the host computer system before the back-end component has completed the second set of initialization operations, provides the configuration data to the host computer system.