Parallel Flash Decoding with Shared-Block Dependency Mitigation
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Solution Overview
Problem
In NAND flash storage, error correcting codes (ECC) face challenges with data dependency issues when decoding multiple constituent codewords in parallel, leading to unpredictable hardware behavior and reduced throughput, especially as the number of parallel decoders increases.
Innovation Solution
A decoder architecture that performs coarse and fine decoding, allowing parallel decoding of multiple codewords sharing common data blocks, with coarse decoding determining error information and correcting errors in one codeword while preventing updates in shared blocks to avoid clashes, and fine decoding correcting errors sequentially if coarse decoding fails.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple decoders are operated in parallel to decode constituent codewords sharing common data blocks, then decoding throughput is improved, but data dependency clashes cause unpredictable hardware behavior and reduce reliability
Solution Approach 1:
The patent applies preliminary action by performing coarse decoding of the first codeword before finalizing updates to shared common data blocks. The error information is determined in advance, and a determination is made whether the shared block will be updated before allowing the second decoder to proceed. This preliminary check prevents data dependency clashes by ensuring that parallel decoders do not simultaneously update the same data blocks, thereby maintaining hardware behavior predictability while preserving parallel throughput benefits.
2Productivity
If the number of parallel component decoders is increased to meet throughput requirements, then decoding capacity is improved, but data dependency problems become more severe
Solution Approach 1:
The patent implements feedback by continuously monitoring whether shared common data blocks are updated during parallel decoding operations. The system determines after each decoding attempt whether updates occurred, and uses this feedback information to control subsequent decoding operations. When updates are detected, the system adjusts the decoding process to prevent conflicts in future iterations. This feedback mechanism enables the system to manage multiple parallel decoders effectively without proportionally increasing data dependency management complexity.
3Reliability
If sequential decoding is used to avoid data dependency clashes, then hardware behavior reliability is improved, but decoding throughput decreases
Solution Approach 1:
The patent applies segmentation by dividing the decoding process into distinct phases: coarse decoding and fine decoding. Coarse decoding is performed in parallel with error information determination, while fine decoding handles the actual error correction with updated common blocks. This segmentation allows different levels of parallelism at different stages - aggressive parallelism in coarse decoding for throughput, and controlled sequential operations in fine decoding for reliability - thereby achieving both high throughput and hardware behavior predictability.
Data Source
AI summary
A memory device can include a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform parallel decoding of codewords. Each of the codewords has a plurality of data blocks, each data block having a number of data bits. The decoding apparatus is configured to decode in parallel two or more codewords, which share a common data block, to determine error information associated with each codeword. For each error, the error information identifies a data block having the and associated error bit patterns. The decoding apparatus is configured to update the two or more codewords based on the identified data blocks having errors and the associated error bit patterns.