Parallel Flash Memory Controller 2D Channel Row Architecture
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Solution Overview
Problem
Current flash memory devices face limitations in interface read/write rate, which restricts their application in high-capacity storage devices, and existing multi-channel controllers do not achieve true parallel operation, leading to inefficiencies and lower data transmission rates.
Innovation Solution
A 2D parallel flash memory controller that enables parallel operations across channels and rows, with instruction parsing units and flash memory control units working in tandem to execute instructions in parallel, increasing data bus bandwidth and allowing simultaneous operations across multiple flash memory chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-channel control is implemented with multiplexed control signal lines, then data bandwidth is increased, but working efficiency decreases due to inability to perform true parallel operations
Solution Approach 1:
The controller is divided into multiple independent control units, each capable of independently controlling a channel. This segmentation allows each control unit to operate autonomously without sharing control signal lines, enabling true parallel operations across multiple channels while maintaining high data bandwidth capacity.
Solution Approach 2:
The patent transitions from 1D sequential control to 2D parallel control by organizing control units in a matrix structure with multiple rows and columns. This dimensional change enables simultaneous control of multiple channels through dedicated control paths, achieving both high bandwidth and high efficiency.
2Speed
If interface read/write rate of flash memory chip is increased, then storage device performance improves, but device complexity increases
Solution Approach 1:
The controller is segmented into multiple independent control units, each handling a channel. This modular segmentation distributes the complexity across multiple simple units rather than requiring one complex centralized controller, enabling high read/write rates through parallel processing while keeping individual unit complexity manageable.
Solution Approach 2:
Each control unit is designed to be self-contained with independent instruction parsing and control capabilities. This self-service design allows each unit to operate autonomously without complex inter-unit coordination, simplifying the overall system architecture while achieving high throughput through parallel operations.
Data Source
AI summary
A parallel flash memory controller, a chip, and a control method thereof are disclosed. First, an on-chip control bus sends flash memory control instructions in parallel to instruction parsing units (211) according to channels. Next, the instruction parsing units store (211) and parse the flash memory instructions corresponding to the flash memory channels, and sequentially send the flash memory control instruction to the flash memory control units (213). Then, the flash memory control units (213) send control instructions to the flash chips in the channels according to rows, and then the control instructions are processed in parallel in flash memory rows. In the present invention, the operations for each channel are performed independently in parallel, the flash memory control units (213) in the channels send the control instructions in series, and meanwhile, in each flash memory row, operations are concurrently performed in parallel. Therefore, the read/write rate of the flash memory is increased for many times, and the bottleneck in adopting flash memory chips to accomplish high-speed and large-capacity storage devices is effectively eliminated.