Parallel Frozen Bit Generation for Flexible Polar Coding
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Solution Overview
Problem
Existing polar coding implementations face challenges in achieving flexibility and efficiency in inserting or removing bits or soft bits from arbitrary positions within blocks, particularly in flexible polar encoders and decoders where K, N, and M vary, leading to high hardware usage and long clock cycles.
Innovation Solution
An electronic device with a bit pattern generator that performs bit pattern generation over multiple clock cycles, using a counter and bank of comparators to process multiple bits simultaneously, and a ROM to store bit patterns, allowing for parallel processing and reduced clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional sequential bit processing is used in polar coding, then hardware usage is reduced, but clock cycles become excessively long
Solution Approach 1:
The patent divides the bit pattern generation process into multiple parallel processing units, where each unit handles a specific subset of bits simultaneously. This segmentation allows the system to process multiple bits in parallel rather than sequentially, significantly reducing the number of clock cycles required while distributing the computational load across multiple hardware components.
Solution Approach 2:
The patent transitions from sequential one-dimensional processing to parallel multi-dimensional processing by introducing multiple processing paths that operate simultaneously. This dimensional change enables the system to handle bit pattern generation for multiple positions at the same time, effectively converting a time-consuming sequential process into a faster parallel operation.
2Adaptability or versatility
If flexible polar encoding is implemented to support varying K, N, and M values, then adaptability is improved, but hardware complexity increases
Solution Approach 1:
The patent designs a universal bit pattern generation apparatus that can handle multiple polar coding configurations (different K, N, and M values) through a single hardware structure. The apparatus uses configurable parameters and shared processing resources that can be adapted to various coding schemes, eliminating the need for separate dedicated hardware for each configuration and thus reducing overall hardware complexity while maintaining flexibility.
Solution Approach 2:
The patent implements dynamic configurability in the hardware through controllable processing units that can adjust their operation based on the required K, N, and M values. This dynamic approach allows the same hardware structure to reconfigure itself for different coding parameters, providing adaptability without requiring multiple fixed hardware designs.
3Productivity
If parallel processing is used to reduce clock cycles, then processing speed is improved, but hardware usage increases
Solution Approach 1:
The patent combines multiple processing functions into a unified parallel processing apparatus that shares common resources such as memory, control logic, and data buses. By merging these functions rather than implementing them as separate independent units, the system achieves parallel processing capability while minimizing the additional hardware overhead through resource sharing and functional integration.
Data Source
AI summary
An electronic device configured to perform polar coding is described. The electronic device includes a bit pattern generator (3403) configured to successively perform a bit pattern generation process over a series (t=┌n/w▴) of clock cycles; and a counter (c, 4203), operably coupled to the bit pattern generator (3403) and configured to count a number of successive bit pattern generation sub-processes over the series (t=┌n/w▴) of clock cycles. The bit pattern generator (3403) is configured to: provide a successive sub-set of (w) bits from a bit pattern vector (bk,n) in each successive t=┌n/w▴ clock cycle; where the bit pattern vector comprises n bits, of which ‘k’ bits adopt a first binary value and n−k bits adopt a complementary binary value.