Parallel Functional Self-Test Controllers for High-Speed Device Validation
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Solution Overview
Problem
The complexity of memory subsystems and other computer components, particularly in high-end systems, makes it challenging to verify design integrity and test communication interfaces effectively due to the overhead of extensive built-in self-test (BIST) logic, which is limited in space and interface testing capabilities.
Innovation Solution
A system with functional self-test controllers configured to run test cases in parallel, arbitrating test traffic through packeted protocol layer interfaces, performing protocol-specific conversions, and verifying responses to ensure comprehensive testing without the need for complex external test equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If extensive built-in self-test (BIST) logic is incorporated to improve testing coverage, then test capability is improved, but device complexity and space requirements increase
Solution Approach 1:
The testing system is segmented into multiple functional self-test controllers that can operate independently and in parallel. Each controller manages specific test cases and devices under test, allowing the testing capability to be distributed across multiple simpler units rather than requiring one complex comprehensive BIST logic block.
Solution Approach 2:
The patent transitions from embedded BIST logic within individual devices to an external test control device that coordinates multiple functional self-test controllers. This dimensional shift moves the testing function from the device level to a system level, enabling comprehensive testing without increasing individual device complexity.
2Productivity
If functional self-test controllers operate in parallel to improve testing efficiency, then productivity is improved, but test traffic arbitration complexity increases
Solution Approach 1:
An arbiter is introduced as an intermediary component between the functional self-test controllers and the packeted protocol layer interfaces. This arbiter manages test traffic from multiple parallel controllers, assigning them to different devices under test and coordinating their operations to avoid conflicts, thereby enabling parallel testing while managing complexity through a dedicated traffic management layer.
3Adaptability or versatility
If protocol specific conversions are performed for each device under test, then adaptability is improved, but processing overhead increases
Solution Approach 1:
The packeted protocol layer interfaces are designed with universal functionality to handle multiple device types and protocols. Rather than requiring separate dedicated conversion paths for each device, the same interface infrastructure supports various protocol conversions through configurable functionality, reducing overall processing overhead while maintaining broad adaptability.
Data Source
AI summary
Aspects include configuring a plurality of functional self-test controllers in a test control device to run a plurality of functional test cases in parallel on a plurality of devices under test. Test traffic is arbitrated between the functional self-test controllers and a plurality of packeted protocol layer interfaces of the test control device. One or more protocol specific conversions are performed between the test traffic and a device-specific packeted protocol of each of the devices under test. Payload checking is performed between the packeted protocol layer interfaces and the devices under test to verify responses of the devices under test to the functional test cases.