Parallel Switch Gate Driver Circuit With Separated Reference Nodes
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Solution Overview
Problem
Existing gate driver assemblies struggle to provide balanced and efficient control of semiconductor switches connected in parallel, leading to unbalanced voltage and current distributions.
Innovation Solution
A power switching assembly with two driver circuits, each supplied via separate internal supply and reference nodes, and connected by separate buffer capacitors, ensuring in-phase gate signals and independent control of each switch, mitigating transient voltage drops across parasitic inductances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a single gate driver output signal is used to drive multiple parallel semiconductor switches, then the current capacity is increased and conduction losses are reduced, but unbalanced voltage and current distributions occur between the parallel switches
Solution Approach 1:
The patent divides a single gate driver into multiple independent driver circuits (first driver circuit, second driver circuit, etc.), each with separate supply nodes and reference nodes. This segmentation allows independent control of gate signals for parallel semiconductor switches, ensuring balanced voltage and current distribution while maintaining the ability to drive multiple switches simultaneously.
2Manufacturing precision
If separate reference nodes are used for each driver circuit, then independent gate voltage control is achieved, but the device complexity increases
Solution Approach 1:
The gate driver is segmented into multiple independent driver circuits, each with its own reference node, supply node, and buffer capacitor. This segmentation provides independent gate voltage control for each parallel semiconductor switch, compensating for variations in parasitic inductances and ensuring balanced operation.
Solution Approach 2:
Each driver circuit is designed with local independence, having its own reference node and buffer capacitor specifically tailored for controlling a particular semiconductor switch. This local quality approach allows each driver circuit to independently compensate for local variations in parasitic inductances, achieving optimal control without requiring complex global coordination.
3Reliability
If buffer capacitors are connected to separate reference nodes, then transient voltage drops are mitigated, but the loss of substance (additional components) increases
Solution Approach 1:
The patent assigns a dedicated buffer capacitor to each driver circuit, connected between the respective supply node and reference node. This segmentation ensures that each driver circuit has its own local energy reservoir to mitigate transient voltage drops independently, improving reliability without requiring complex shared capacitor networks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables symmetric switching and independent gate voltage control for each semiconductor switch, preventing harmful compensation currents and maintaining efficient operation even with varying parasitic inductances.
Implementation Method 1
A first buffer capacitor is electrically connected between the first internal supply node and the first reference node. A second buffer capacitor electrically connected between the second internal supply node and the second reference node.
Data Source
AI summary
A power switching assembly includes a first driver circuit and a second driver circuit. The first driver circuit is supplied via a first internal supply node and a first reference node and drives a first gate signal. The second driver circuit is supplied via a second internal supply node and a second reference node and drives a second gate signal. The first gate signal and the second gate signal are configured to be in phase with each other. The first reference node and the second reference node are separated. A first buffer capacitor is electrically connected between the first internal supply node and the first reference node. A second buffer capacitor electrically connected between the second internal supply node and the second reference node.