Parallel Gate Driver Circuit With Separated References
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Solution Overview
Problem
Existing gate driver circuits struggle to provide balanced and efficient control of semiconductor switches connected in parallel, leading to unbalanced voltage and current distributions, which can result in increased conduction losses and reduced performance.
Innovation Solution
A power switching assembly comprising two gate driver circuits with separate internal supply nodes and reference nodes, each equipped with a buffer capacitor, ensures independent and balanced gate drive loops by maintaining separate reference potentials and using buffer capacitors to manage transient voltages, thereby preventing harmful compensation currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple semiconductor switches are connected in parallel to increase current capacity, then the current handling capability is improved, but unbalanced voltage and current distributions occur between the switches
Solution Approach 1:
The gate driver circuit is segmented into multiple independent driver circuits (first driver circuit, second driver circuit, etc.), each controlling a respective semiconductor switch. Each driver circuit has its own internal supply node and reference node, creating independent control channels that prevent cross-interference and ensure balanced current distribution among parallel switches.
Solution Approach 2:
Each driver circuit is provided with localized buffer capacitors (first buffer capacitor, second buffer capacitor, etc.) connected between its internal supply node and reference node. These local capacitors provide individual transient current compensation for each switch, ensuring uniform switching characteristics and balanced current sharing across all parallel-connected switches.
2Device complexity
If a single gate driver output signal is used to drive multiple parallel semiconductor switches, then the device complexity is reduced, but harmful compensation currents occur due to transient voltage drops
Solution Approach 1:
The single gate driver is segmented into multiple independent driver circuits, each with separate reference nodes. This segmentation prevents the formation of compensation current loops that would occur with a shared reference node, as each driver now has its own independent reference potential and buffer capacitor, eliminating the harmful circulating currents.
3Device complexity
If reference nodes are shared between driver circuits, then the device complexity is reduced, but transient voltage drops cause unbalanced switching
Solution Approach 1:
The shared reference node is segmented into multiple separate reference nodes (first reference node, second reference node, etc.), each dedicated to a specific driver circuit. This segmentation isolates the reference potentials from each other, preventing transient voltage drops in one circuit from affecting others, thereby ensuring symmetric and balanced switching across all parallel semiconductor switches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables independent control of each semiconductor switch, reducing conduction losses and ensuring symmetric switching by decoupling gate drive loops from transient voltage drops, thus improving the overall efficiency and balance of parallel-connected semiconductor switches.
Implementation Method 1
A first buffer capacitor is electrically connected between the first internal supply node and the first reference node. A second buffer capacitor is electrically connected between the second internal supply node and the second reference node.
Data Source
Figure 1A~1B
Figure 2
Figure 3
AI summary
A power switching assembly (900) includes a first driver circuit (110) and a second driver circuit (120). The first driver circuit (110) is supplied via a first internal supply node (VDD1) and a first reference node (VSS1) and drives a first gate signal. The second driver circuit (120) is supplied via a second internal supply node (VDD2) and a second reference node (VSS2) and drives a second gate signal. The first gate signal and the second gate signal are in phase. The first reference node (VSS1) and the second reference node (VSS2) are separated. A first buffer capacitor (131) is electrically connected between the first internal supply node (VDD1) and the first reference node (VSS1). A second buffer capacitor (132) electrically connected between the second internal supply node (VDD2) and the second reference node (VSS2).