Parallel Gate Driving Circuit for LCD Signal Delay and BM Width
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Solution Overview
Problem
In large liquid crystal display (LCD) apparatuses, gate driving signals are delayed due to longer gate lines and a greater number of thin film transistors, deteriorating the operational properties of the gate driving circuit and increasing the Black Matrix (BM) width, which affects the symmetric structure and display performance.
Innovation Solution
A gate driving circuit with multiple stages connected in parallel, where odd-numbered stages output gate driving signals to odd-numbered gate lines in response to a first clock signal and even-numbered stages output signals to even-numbered gate lines in response to a second clock signal with an opposite phase, improving signal delivery and reducing BM width by enhancing operational properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If the gate driving circuit is arranged in parallel with the data driving circuit integrated into the peripheral areas of the LCD panel to achieve a symmetric structure, then the structural symmetry is improved, but the Black Matrix (BM) width is increased
Solution Approach 1:
The patent applies asymmetry by positioning the gate driving circuit and data driving circuit at different locations within the peripheral areas of the LCD panel, rather than arranging them symmetrically. This asymmetric arrangement allows for optimized space utilization that reduces the Black Matrix width while maintaining functional requirements.
Solution Approach 2:
The patent redistributes the driving circuits along the peripheral boundaries of the panel in a linear arrangement rather than placing them in symmetric positions. This dimensional reorganization of circuit placement optimizes the use of peripheral space and minimizes the Black Matrix area.
2Area of stationary object
If the gate lines are made longer to cover larger display areas, then the display area is increased, but the gate driving signals are delayed due to longer gate lines and greater number of TFTs
Solution Approach 1:
The gate driving circuit is divided into multiple independent stages that can operate in parallel. Each stage drives a specific portion of the gate lines, allowing simultaneous signal generation across different segments. This segmentation reduces the cumulative delay by eliminating sequential propagation through a single long chain of TFTs.
Solution Approach 2:
Multiple gate driving stages are prepared in advance to simultaneously drive different gate lines. Instead of sequentially activating gates along a single line, the system pre-configures multiple driving points that can initiate signal propagation at the same time, effectively reducing the overall signal delay across the display area.
Data Source
AI summary
A liquid crystal display apparatus including a gate driving circuit disposed on a liquid crystal display is provided. The apparatus further includes a data driving chip, disposed on the liquid crystal display panel, to apply data driving signals to data lines. The gate driving circuit includes a plurality of stages connected to one another in parallel. The odd-numbered stages of the stages each apply gate driving signals to odd-numbered gate lines of the gate lines, in response to a first clock signal and the even-numbered stages of the stages each apply the gate driving signals to even-numbered gate lines of the gate lines, in response to a second clock signal having an opposite phase from a phase of the first clock signal.