Parallel Gate and Conductive Pattern Layout for Lower Resistance
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Solution Overview
Problem
Semiconductor devices with higher resistance experience a decrease in operating speeds as technology advances, necessitating a reduction in resistance during layout design of standard cells.
Innovation Solution
Implementing parallel connections of conductive patterns, including bottom, middle, and top conductive patterns, along with parallel connections of poly-material patterns, to reduce overall resistance and increase operating speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional layout design is used, then device structure is simple, but resistance is high and operating speed decreases
Solution Approach 1:
The conductive patterns are divided into multiple parallel segments (first, second, third conductive patterns) that extend in different directions. This segmentation allows current to flow through multiple parallel paths, reducing overall resistance while maintaining a compact layout structure that fits within standard cell boundaries.
Solution Approach 2:
The conductive patterns transition from single-direction linear paths to multi-dimensional arrangements. The first conductive pattern extends in a first direction, the second in a second direction, and the third in a third direction, creating a three-dimensional conductive network that reduces resistance without increasing layout area.
2Reliability
If parallel connections are implemented, then resistance is reduced, but layout complexity increases
Solution Approach 1:
The poly-material patterns serve multiple functions: they act as both conductive interconnects and as structural elements that define the standard cell boundaries. The gate electrodes also serve dual purposes as both transistor control elements and as additional conductive paths that contribute to the parallel connection network, reducing the need for separate dedicated interconnect structures.
Solution Approach 2:
Multiple conductive functions are merged into unified structures. The gate electrodes are combined with the parallel conductive pattern network, and the poly-material patterns are integrated to provide both mechanical support and electrical conduction. This merging reduces the total number of separate layers and structures needed, simplifying the overall layout despite the complex electrical connections.
Data Source
AI summary
A method of manufacturing a semiconductor device includes: forming first through fourth active regions extending in parallel in a substrate; forming a first gate electrode and a first conductive pattern each extending across each of the first through fourth active regions; forming a first plurality of vias overlying the first gate electrode; forming a second plurality of vias overlying the first conductive pattern; and electrically connecting the first gate electrode in parallel with the first conductive pattern through the first and second pluralities of vias.