Parallel Semiconductor Gate Interconnect Layout for Synchronized Switching
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Solution Overview
Problem
Existing semiconductor apparatuses face challenges in aligning the timing of switching operations for multiple semiconductor devices, leading to timing deviations when simultaneously switching these devices.
Innovation Solution
The semiconductor apparatus is designed with an interconnect pattern that connects control electrodes of semiconductor devices through equal-length interconnects, ensuring synchronized switching operations and reducing timing deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional interconnect patterns are used to connect control electrodes of multiple semiconductor devices, then the device structure is simple and easy to manufacture, but timing deviations occur during simultaneous switching operations
Solution Approach 1:
The patent changes the parameter of interconnect length to be equal across all control electrode connections. By designing the interconnect pattern such that all paths from the control signal source to each semiconductor device's gate electrode have equal length, the signal propagation time is equalized, thereby achieving simultaneous switching without timing deviations while maintaining manufacturing feasibility through systematic layout design
2Reliability
If equal-length interconnects are used to synchronize switching operations, then timing alignment is improved, but the interconnect pattern design becomes more complex
Solution Approach 1:
The patent applies asymmetry in the overall interconnect layout design to achieve symmetry in signal propagation characteristics. The interconnect pattern may have an asymmetric physical arrangement but is designed so that the total path length from the control signal source to each gate electrode remains equal, thereby achieving switching synchronization without requiring a perfectly symmetric layout, which simplifies the design process while maintaining reliability
Data Source
Figure 1A~1B
Figure 2A~2C
Figure 3A~3B
AI summary
A semiconductor apparatus includes three or more semiconductor devices connected in parallel with each other and an interconnect substrate arranged on the semiconductor devices, wherein the semiconductor devices have respective control electrodes and are switched by a voltage applied to the control electrodes, wherein the interconnect substrate includes an insulating layer and a first interconnect pattern arranged on an opposite side of the insulating layer from the semiconductor devices and connecting the control electrodes of the semiconductor devices, wherein the first interconnect pattern includes a same number of interconnects of equal length as the semiconductor devices, and a voltage input point configured to receive a voltage applied to the control electrodes via the interconnects of equal length, and wherein the control electrodes of the semiconductor devices are connected to the voltage input point only by the interconnects of equal length, which extend in different directions from the voltage input point.