Parallel Gate-Control Transistors for ON Resistance and Active Clamp
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Solution Overview
Problem
Semiconductor devices with insulation gate-type transistors face a trade-off in achieving excellent ON resistance and active clamp capability, as increasing the channel area reduces ON resistance but degrades active clamp capability due to temperature rise, while reducing the channel area improves active clamp capability but increases ON resistance.
Innovation Solution
A semiconductor device with two insulation gate-type transistors and a control circuit that allows the first transistor to be in an ON state during normal operation and the second transistor to handle active clamp operations, reducing ON resistance and improving active clamp capability by managing current paths and counter electromotive force.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the area of channel is increased, then the ON resistance is reduced, but the active clamp capability is reduced due to sharp temperature rise
Solution Approach 1:
The patent divides the single transistor channel into two separate channels (first channel and second channel) that can be independently controlled. The first transistor handles normal operation current while the second transistor is dedicated to active clamp operation. This segmentation allows each channel to be optimized for its specific function, enabling low ON resistance through the first channel during normal operation while the second channel provides robust active clamp capability without temperature rise issues.
Solution Approach 2:
The patent implements dynamic control of the two transistors through a control circuit that switches between normal operation mode and active clamp mode. During normal operation, the first transistor is ON and the second is OFF. During active clamp operation, the control circuit switches to turn OFF the first transistor and turn ON the second transistor. This dynamic switching allows the system to adapt its characteristics based on operational requirements, achieving both low ON resistance and excellent active clamp capability at different times.
2Reliability
If the area of channel is reduced, then the active clamp capability is improved, but the ON resistance is increased
Solution Approach 1:
The patent segments the current handling function between two separate transistors. The second transistor can be designed with channel dimensions optimized specifically for active clamp operation, providing robust clamp capability. Meanwhile, the first transistor handles the normal operation current with channel dimensions optimized for low ON resistance. This functional segmentation eliminates the need to compromise either parameter.
Solution Approach 2:
The control circuit dynamically switches between the two transistors based on operational mode. During active clamp operation, the system dynamically activates the second transistor which is optimized for clamp capability, while keeping the first transistor inactive. During normal operation, the switching is reversed. This dynamic allocation allows the system to achieve optimal performance for each specific operational requirement without compromise.
Data Source
AI summary
A semiconductor device includes first and second insulated-gate transistors in parallel with each other, a charger-discharger, and a gate voltage correction circuit. The charger-discharger can perform first control to charge both of the gates of the first and second transistors, second control to discharge both of the gates of the first and second transistors, and third control to charge one of the gates of the first and second transistors. The gate voltage correction circuit corrects the gate voltages of the first and second transistors to eliminate the difference between those voltages in at least one of the first control, the second control, and protection operation in which the first and second transistors are forcibly kept off.