Parallel GHASH Circuit for Continuous Ciphertext Authentication
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Solution Overview
Problem
Existing GHASH authentication methods struggle to process data streams without intervals, such as those used in PCIe-Gen6 and CXL protocols, which require high throughput and parallel calculation architectures due to the absence of gaps between data units like flits, and handle out-of-order AAD and ciphertext inputs.
Innovation Solution
A Galois hash authentication-based circuit with additional authentication data, ciphertext calculation, and bubble processing circuits, along with a controller, enables parallel processing of data streams by shifting and calculating data blocks in a manner that accommodates out-of-order inputs and continuous data flow without blocking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential processing is used for GHASH operations on data packets with intervals, then processing simplicity is maintained, but data throughput is limited and cannot meet high-speed protocols like CXL
Solution Approach 1:
The patent divides the data stream into discrete data blocks (e.g., 128-bit blocks) that can be processed independently in parallel. Each data block is handled by separate processing units within the GHASH circuit, allowing simultaneous computation without requiring complex inter-block coordination, thus achieving high throughput while controlling complexity.
Solution Approach 2:
The patent transitions from sequential time-based processing to spatial parallel processing by implementing multiple calculation units that operate simultaneously on different data blocks. This dimensional shift from serial to parallel architecture enables the circuit to meet the high throughput requirements of protocols like CXL (128 Gbps, 256 Gbps) while maintaining manageable complexity through modular design.
2Productivity
If GHASH operations are performed on continuously transmitted data streams without intervals, then data flow blocking is avoided, but processing complexity increases due to lack of natural synchronization points
Solution Approach 1:
The patent implements a buffering mechanism that preliminarily stores incoming data blocks before processing. This buffer acts as a synchronization point that decouples the continuous data stream from the parallel processing units, allowing the circuit to handle continuous flow without requiring complex real-time coordination between processing stages.
Solution Approach 2:
The patent introduces intermediate registers and control logic that mediate between the continuous data stream input and the parallel processing units. These intermediaries buffer and regulate data flow, providing natural synchronization points without blocking the overall continuous flow, thus managing complexity while maintaining high throughput.
3Productivity
If AAD and ciphertext are processed in parallel input order, then processing speed is improved, but correctness may be compromised compared to sequential packet-based processing
Solution Approach 1:
The patent segments the authentication process into distinct functional units: one for processing additional authentication data (AAD) and another for processing ciphertext. Each segment handles its designated data type independently in parallel, then combines results through a controlled mixing operation that ensures mathematical correctness regardless of input order, thus maintaining reliability while achieving speed improvement.
Solution Approach 2:
The patent employs parameter-based control where the processing order and mixing operations are dynamically adjusted based on data type parameters. By changing operational parameters (such as which processing unit receives which input and how results are combined) rather than the fundamental processing architecture, the circuit maintains authentication correctness while enabling parallel input processing.
Data Source
AI summary
The disclosure provides a Galois hash authentication-based circuit. An additional authentication data calculation circuit receives the first data block in the data stream and performs calculation according to the first data block, and shifts the calculation result to the left to generate a first output. A ciphertext calculation circuit includes k first calculation units, used to receive in parallel the second data blocks in the data stream in each round of calculation of the ciphertext calculation circuit, and perform parallel calculation on each data block received to generate a second output. The bubble processing circuit receives the first quantity of the third data blocks after the last round of calculation of the ciphertext calculation circuit and performs calculation to generate a third output. A message authentication code is calculated according to the first output, the second output, and the third output.