Parallel GPS Correlator Architecture for High-Speed Signal Processing
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Solution Overview
Problem
Conventional GPS receiver correlators suffer from low speed and high power consumption due to serial data processing and require multiple correlators for each satellite channel, making them unsuitable for low-power applications and limiting their performance.
Innovation Solution
A correlator with a parallel architecture using 64-bit Doppler frequency and C/A code generators, along with a buffer and detector, enables high-speed processing and shared hardware design for multiple channels, reducing power consumption and chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If serial data processing is used in conventional correlators, then device complexity is reduced, but processing speed deteriorates
Solution Approach 1:
The patent divides the serial data stream into parallel segments using a parallelizer. The serial-to-parallel converter splits incoming serial data into multiple parallel data streams, allowing simultaneous processing of multiple code phases. This segmentation enables the correlator to process multiple satellite codes in parallel, dramatically increasing processing speed without proportionally increasing overall device complexity.
Solution Approach 2:
The patent transitions from one-dimensional serial processing to multi-dimensional parallel processing by adding the time dimension through pipelined architecture. Multiple correlation operations are performed simultaneously at different pipeline stages, effectively adding a temporal dimension to the processing. This dimensional transformation allows the system to achieve high-speed processing while maintaining manageable device complexity through structured organization.
2Measurement precision
If multiple correlators are used for each satellite channel, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent implements a shared correlator architecture where a single correlator unit serves multiple satellite channels through time-multiplexed operation. The correlator is configured to process different satellite codes sequentially, with the parallelizer enabling multiple code phases to be processed in parallel within each time slot. This universal design maintains measurement precision for all channels while significantly reducing power consumption compared to having dedicated correlators for each channel.
Solution Approach 2:
The patent employs periodic switching between different satellite channel processing using a channel selector. The correlator alternates between processing different satellite codes in a periodic manner, with each channel receiving dedicated processing time slots. This periodic action ensures that each satellite channel maintains its detection accuracy while the overall system consumes less power than continuous operation of multiple parallel correlators.
3Productivity
If high-speed processing is implemented, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent performs preliminary processing of the incoming signal by pre-generating local replica codes and pre-organizing them in parallel structures before correlation. The parallelizer is configured to pre-segment the data stream into parallel paths, and the pipelined correlator pre-computes correlation values for multiple code phases simultaneously. This preliminary action enables high-speed processing throughput while keeping the overall circuit complexity manageable by distributing computations across organized parallel stages.
Solution Approach 2:
The patent implements dynamic pipeline control where the correlator can adaptively adjust its processing rate and parallelism level based on signal conditions and channel requirements. The pipelined architecture allows dynamic allocation of processing resources, enabling the system to achieve high productivity when needed while reducing operational complexity under normal conditions. This dynamic operation balances throughput requirements with device complexity constraints.
Data Source
AI summary
The present invention discloses correlation architecture in the application of full-digital GPS (Global Positioning System) receivers. According to the present invention, a satellite C/A code generator is employed to generate N-bit parallel code data at a time, and a Doppler frequency generator is used to generate N-bit parallel Doppler frequency data at a time. Signals received by the receiver can be temporarily stored in a buffer that provides N-bit parallel reception data to a correlation circuit. In the correlation circuit, a N-bit multiplier is used to multiply the N-bit reception data by the N-bit C/A code data and the N-bit Doppler frequency data to generate multiplication results. The N-bit multiplication results are thereafter summed up in parallel by a digital summator. Accordingly, the correlator of the present invention can improve circuit performance and save the required cost.