Parallel Half-Bridge Leg Control for Current Balancing and Low dV/dt
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Solution Overview
Problem
Existing power semiconductor bridge leg arrangements face issues with voltage overshoot, oscillatory behavior, and rate of change of voltage increase/decrease during switching events, which lead to electromagnetic interference and increased switching losses, and current imbalance due to device characteristic variations and aging.
Innovation Solution
A power semiconductor bridge leg arrangement with multiple parallel half-bridge modules, each with dedicated inductances and active gate driving, where the control circuit generates individual gating signals and introduces timing skew between switching events to balance currents and reduce voltage change rates, allowing for robust operation regardless of impedance matching and device aging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DC-loop inductances and inductances of the switching arrangement are designed to be as low as possible, then switching speed is improved, but voltage overshoot and oscillatory behavior increase
Solution Approach 1:
The patent divides a single half-bridge switching arrangement into multiple parallel half-bridges (first, second, and third half-bridges). Each half-bridge has its own switching elements and inductance, allowing the system to segment the switching action and reduce voltage overshoot and oscillations by distributing the switching stress across multiple parallel paths while maintaining fast switching speed.
2Object-generated harmful factors
If gate resistances are increased to reduce rate of change of current during turn-off, then voltage overshoot is reduced, but switching losses increase
Solution Approach 1:
The patent segments the switching function across multiple parallel half-bridges, allowing each switching element to operate with optimized gate resistance values. This segmentation enables reduced dI/dt through proper timing control while avoiding the need for excessively high gate resistances that would increase switching losses.
Solution Approach 2:
The control circuit is configured to activate switching elements in a specific sequence, with preliminary action taken by turning on certain switches before others. This staged activation allows current to be redistributed gradually through the parallel half-bridges, reducing dI/dt without requiring high gate resistances.
3Object-generated harmful factors
If multiple parallel half-bridges are used to reduce rate of change of voltage, then voltage change rate is reduced, but current balancing between half-bridges becomes problematic
Solution Approach 1:
The control circuit implements preliminary action by pre-configuring the switching states of individual half-bridges before main switching events. This allows the system to anticipate and compensate for current imbalances by adjusting the timing and sequence of switch activation, ensuring current balancing while maintaining reduced dV/dt through the parallel architecture.
Solution Approach 2:
The control circuit monitors the operational state of each half-bridge and adjusts switching signals in real-time to maintain current balance. This feedback mechanism detects current distribution across parallel half-bridges and modifies gate drive signals to equalize current flow, solving the current balancing problem inherent in multi-parallel configurations.
4Stability of the object's composition
If delay based active gate driving with interphase transformers is used, then current balancing is achieved, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the interphase transformer component from the system while retaining current balancing functionality. By using direct parallel connection of half-bridges with control circuit-based timing adjustment, the solution removes the complex magnetic coupling components while achieving the same current balancing effect through electronic control.
Solution Approach 2:
The patent replaces the mechanical/magnetic coupling mechanism (interphase transformers) with an electronic control mechanism. The control circuit uses timing-skewed gate drive signals to achieve current balancing, substituting the physical transformer-based current equalization with an electronically controlled timing-based approach, thereby reducing device complexity.
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
The invention refers to a power semiconductor bridge leg arrangement (1), comprising a first connection point (2) and a second connection point (3), which are to be connected to a DC-voltage source (4), and a midpoint (5) as output, a switching arrangement (10) having a number of semiconductor switching elements (6) connected between the first connection point (2) and the second connection point (3), and a control circuit (7) for controlling the number of semi-conductor switching elements (6) of the switching arrangement (10). The invention is characterized in that the switching arrangement (10) comprises at least two individual power semiconductor half-bridge modules (11, 12, 13) connected in parallel between the first connection point (2) and the second connection point (3), each half-bridge module (11, 12, 13) comprising a high-side semiconductor switch (11H, 12H, 13H) and a low-side semiconductor switch (11L, 12L, 13L) being connected to a half-bridge midpoint (11M, 12M, 13M), where the half-bridge midpoint (11M, 12M, 13M) is connected to the midpoint (5) of the bridge leg arrangement(1) with a dedicated designed inductance (L1, L2, L3). Furthermore, the control circuit (7) is adapted to individually control the switch operations of each semiconductor switch (11H, 11L, 12H, 12L, 13H, 13L) of the at least two individual power semiconductor half-bridge modules (11, 12, 13).