Parallel Hash-Chain Processor for IoT Digital Signatures
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Solution Overview
Problem
Digital signature computations, particularly hash-chain computations, are too slow for resource-constrained devices in the Internet of Things (IoT) due to the high resource requirements of existing cryptographic algorithms like RSA and (EC)DSA, which are threatened by quantum computers, and require optimization for efficient execution on embedded devices.
Innovation Solution
A hardware device with a processor that computes multiple chained hash functions in parallel using a single instruction and multiple data (SIMD) operations, optimized for small input sizes, where each hash function operates on a dedicated data unit, allowing concurrent execution and reducing memory latency by using counters to manage varying chain lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional cryptographic algorithms (RSA, (EC)DSA) are used for digital signatures, then security is provided, but resource requirements are too high for IoT devices
Solution Approach 1:
The patent segments the hash-chain computation into multiple parallel chains, where each chain is processed independently. This allows the computational workload to be divided into smaller units that can be executed in parallel, reducing the overall resource requirements while maintaining security through the cryptographic strength of individual hash functions.
Solution Approach 2:
The patent introduces parallelism as a new dimension for computation by implementing multiple hash chains simultaneously. Instead of sequentially processing a single hash chain, the system processes multiple chains in parallel, effectively adding a temporal and spatial dimension to the computation that reduces resource usage per unit of cryptographic work.
2Reliability
If traditional cryptographic algorithms are used for digital signatures, then security is provided, but computation speed is too slow for resource-constrained devices
Solution Approach 1:
The hash-chain computation is segmented into multiple independent chains that can be processed in parallel. Each chain maintains its cryptographic integrity while the overall computation speed increases proportionally to the number of parallel chains executed simultaneously on the resource-constrained device.
Solution Approach 2:
The patent pre-computes and stores intermediate hash values in a Merkle tree structure, allowing verification operations to skip redundant computations. This preliminary action stores computational results in advance, significantly speeding up verification speed while maintaining security through the cryptographic properties of the hash functions.
3Use of energy by moving object
If hash-chain computations are performed sequentially, then resource requirements are reduced, but computation time increases
Solution Approach 1:
The computation is segmented into multiple parallel hash chains, each requiring minimal resources individually but collectively providing substantial computational throughput. This segmentation allows the device to maintain low per-chain resource usage while achieving fast overall computation through parallel execution of multiple chains.
Solution Approach 2:
The patent implements continuous parallel computation across multiple hash chains, ensuring that the processor remains continuously utilized without idle cycles. By keeping multiple computational streams active simultaneously, the system eliminates wasted time between sequential operations while maintaining efficient resource usage through optimized parallel execution.
4Speed
If multiple hash functions are computed in parallel, then computation speed increases, but device complexity increases
Solution Approach 1:
The patent implements a universal hash function core that can process multiple hash chains using the same cryptographic algorithm. This multi-functional design allows a single hardware or software module to handle parallel computations, reducing device complexity compared to implementing separate dedicated units for each hash chain while still achieving high computation speed through parallelism.
Data Source
AI summary
Various embodiments relate to a hardware device configured to compute a plurality of chained hash functions in parallel, including: a processor implementing p hash functions configured to operate on a small input, where p is an integer; a data unit connected to the plurality of hash functions, configured to store the outputs of plurality of hash functions that are then used as the input to a next round of computing the hash function, wherein the processor receives a single instruction and p small data inputs, and wherein each of the p hash functions are used to perform a chained hash function operation on a respective small input of the p small inputs.