Parallel Hash Compression Accelerator With Ordered Output Buffering
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Solution Overview
Problem
Hash-based compression in software is less efficient compared to dedicated hardware, necessitating methods to accelerate hash-based compression in microprocessors for improved performance.
Innovation Solution
A compression accelerator in a microprocessor that utilizes a Finite-State Machine (FSM) to receive substrings, map them to hash indices, and direct a selector to match paths, transmitting no-match or match messages with offsets to facilitate efficient hash-based compression, allowing out-of-order calculation results to be recorded and compressed in the original order.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hash-based compression is implemented in software, then flexibility and adaptability are maintained, but processing speed and efficiency deteriorate
Solution Approach 1:
The patent replaces software-based hash computation with dedicated hardware circuits including hash functions, matchers, and a hash table. This substitution of mechanical/computational system with specialized hardware architecture achieves acceleration of hash-based compression while maintaining the essential functionality through parallel processing capabilities.
Solution Approach 2:
The compression accelerator is divided into multiple independent functional modules: multiple hash functions (e.g., 4 hash functions), multiple matchers, a hash table, and an intermediary buffer. Each module operates independently and in parallel, enabling simultaneous processing of multiple substrings and improving overall compression throughput.
2Productivity
If multiple hash requests are processed in parallel, then processing throughput is improved, but maintaining original order of compression becomes more difficult
Solution Approach 1:
An intermediary buffer is introduced as a mediator between the parallel processing units (hash functions and matchers) and the compression output. This buffer temporarily stores compression results with their corresponding position information, enabling results from parallel operations to be reorganized and output in the original sequence without compromising parallel processing efficiency.
3Measurement precision
If the hash table size is increased to reduce conflicts, then matching accuracy is improved, but memory usage and access time increase
Solution Approach 1:
The patent employs multiple hash functions (e.g., 4 different hash functions) that map substrings to different positions in the hash table. This multi-dimensional approach distributes hash conflicts across different dimensions, reducing collision rates and improving matching accuracy without requiring a proportionally larger hash table, thus balancing accuracy with access time efficiency.
Data Source
AI summary
The invention introduces a method for accelerating hash-based compression, performed in a compression accelerator, comprising: receiving, by a plurality of hash functions, a plurality of substrings from an FSM (Finite-State Machine) in parallel; mapping, by each hash function, the received substring to a hash index and directing a selector to connect to one of a plurality of match paths according to the hash index; transmitting, by a matcher of each connected match path, a no-match message to the FSM when determining that a hash table does not contain the received substring; and transmitting, by the matcher of each connected match path, a match message and a match offset of the hash table to the FSM when determining that the hash table contains the received substring, wherein the match offset corresponds to the received substring.