Parallel IC Test System Using Segmented Wafer Zones
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Solution Overview
Problem
Current integrated circuit testing methods are limited by the number of testing channels, allowing only serial testing of one die at a time, leading to prolonged testing times and high costs due to the need for frequent probe movements and limited testing frequency.
Innovation Solution
A parallel testing method and system that delivers the same stimulation to multiple identical microelectronic circuits on a common substrate, comparing their outputs in parallel to identify flawed devices, without a significant increase in testing channels, using a combination of input and output distribution paths, comparison apparatuses, and power supply circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If serial testing of one die at a time is performed, then testing channel cost is controlled, but testing time increases and productivity decreases
Solution Approach 1:
The wafer is divided into multiple zones, and the testing process is segmented into multiple passes. In each pass, a subset of dice within a specific zone is tested in parallel using available testing channels. The testing sequence is segmented into first pass, second pass, and subsequent passes, allowing systematic parallel testing across the entire wafer while managing channel resources efficiently.
Solution Approach 2:
The invention introduces a spatial dimension to parallel testing by selecting dice from different zones simultaneously for testing. Instead of testing dice sequentially in a single line, the system tests multiple dice across different spatial zones in parallel, effectively utilizing the two-dimensional wafer layout to increase throughput without proportionally increasing testing channel requirements.
2Productivity
If multi-site parallel testing is performed, then testing time is reduced, but the number of testing channels must be increased which raises equipment cost
Solution Approach 1:
The wafer is divided into multiple zones, and the testing process is segmented into multiple passes. In each pass, a subset of dice within a specific zone is tested in parallel using available testing channels. The testing sequence is segmented into first pass, second pass, and subsequent passes, allowing systematic parallel testing across the entire wafer while managing channel resources efficiently.
Solution Approach 2:
Instead of testing all dice in parallel simultaneously (excessive action), the system tests a partial subset of dice in each pass using the available testing channels. This partial parallel testing approach achieves significant throughput improvement while avoiding the prohibitive cost of providing testing channels for all dice simultaneously.
3Productivity
If probe moves from one die to another die, then different dice can be tested, but testing time is wasted during movement
Solution Approach 1:
The system maintains continuous useful action by testing multiple dice in parallel without requiring the probe to move between them during the testing phase. Once the probe establishes contact with a zone, multiple dice within that zone are tested simultaneously and continuously, eliminating idle movement time between sequential die tests.
Solution Approach 2:
The wafer is divided into multiple zones, and the testing process is segmented into multiple passes. In each pass, a subset of dice within a specific zone is tested in parallel using available testing channels. The testing sequence is segmented into first pass, second pass, and subsequent passes, allowing systematic parallel testing across the entire wafer while managing channel resources efficiently.
Data Source
AI summary
A method, apparatus and system for integrated circuit testing, wherein a plural number of devices under test (DUTs) and a plural number of comparison apparatuses are placed on a common substrate. The DUTs all operate under the same input stimulation and each produce its own operation output. The outputs are compared by the comparison apparatuses to generate comparison characteristics which are used to filter-out the failed devices. This invention lowers the testing cost, shortens time to product mass-production, and lowers the miss rate of failed devices passed as good ones.