Parallel IC Testing on Printed Substrates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In high-volume, low-cost manufacturing of integrated circuits using roll-to-roll or sheet-to-sheet printing, the testing for correct operation of integrated circuits becomes a significant overhead due to the need for individual testing of each circuit, which increases costs and reduces efficiency.
Innovation Solution
The method involves forming an array of circuit elements with integrated circuits and testing circuits, allowing for parallel testing of multiple circuits, combining test results to produce a single signal indicating correct or faulty operation, and separating the array to discard faulty circuits, thereby reducing testing time and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If individual testing of each integrated circuit is performed, then testing accuracy is improved, but productivity deteriorates due to increased testing time and costs
Solution Approach 1:
The substrate is divided into multiple arrays, and each array is tested independently using separate testing circuits. This segmentation allows parallel testing of multiple circuits simultaneously, improving productivity while maintaining testing accuracy through dedicated testing paths for each array.
Solution Approach 2:
Multiple testing circuits are combined into a single integrated testing system that operates in parallel. The testing circuits are integrated with the substrate and can simultaneously test multiple integrated circuits, achieving both high accuracy and high productivity through combined parallel operation.
2Reliability
If individual testing of each integrated circuit is performed, then testing reliability is improved, but loss of time increases due to sequential testing processes
Solution Approach 1:
Testing circuits are pre-integrated with the integrated circuits on the substrate during manufacturing, so that testing can begin immediately after fabrication without requiring separate setup or alignment steps. This preliminary integration eliminates setup time and enables immediate parallel testing.
Solution Approach 2:
The parallel testing architecture enables continuous testing of multiple circuits simultaneously without interruption. While one array is being tested, other arrays are also being tested in parallel, eliminating idle time and maintaining continuous productive action throughout the testing process.
3Productivity
If parallel testing of multiple integrated circuits is implemented, then productivity is improved, but device complexity increases due to additional testing circuits
Solution Approach 1:
The testing circuits are designed with multi-functionality, serving both as part of the integrated circuit functionality and as testing circuits. This universal design reduces the need for separate dedicated testing components, thereby reducing overall device complexity while maintaining high testing throughput.
Solution Approach 2:
The testing circuits are nested within the substrate structure, with multiple testing circuits arranged in a hierarchical pattern where smaller testing units are contained within larger array structures. This nesting approach optimizes space utilization and reduces the overall footprint of the testing system, managing complexity through efficient spatial organization.
Data Source
AI summary
Integrated circuits (12) are manufactured by printing an array of circuit elements CE each containing an integrated circuit and associated testing circuitry (14). A plurality of integrated circuits within the array are tested in parallel to generate a corresponding plurality of individual test result signals. These individual test result signals are combined to form a combined test result signal indicating whether any of the plurality of integrated circuits tested in parallel operated incorrectly during their testing. If the combined test result signal indicates any faulty integrated circuits, then the entire plurality of integrated circuits (e.g. an entire row or column) may be discarded. The array of tested integrated circuits are then separated into discrete integrated circuits and are also separated from their testing circuit. Contacts (16, 18, 20) providing power signals, clock signals, and the reading of the combined test result signals are located at the periphery of a substrate sheet onto which the array of circuit elements are printed.