Parallel IF Demodulator Filtering for High-Bandwidth Receivers
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Solution Overview
Problem
Superheterodyne radio receivers face challenges in handling high bandwidth signals due to large sample rates required by analog-to-digital converters, which existing hardware technologies struggle to implement without increasing cost, complexity, and power consumption.
Innovation Solution
The method involves translating RF signals to an intermediate frequency, converting to digital samples at four times the IF, dividing samples into even and odd sets, and using parallel quadrature demodulators and digital filters to produce a baseband complex signal at half the sampling frequency, reducing processing and hardware requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the ADC sampling rate is increased to handle high bandwidth signals, then the signal bandwidth capability is improved, but the hardware cost, complexity, and power consumption increase
Solution Approach 1:
The patent divides the high-rate ADC output stream into two separate lower-rate streams by separating even and odd samples. Each stream is processed independently by parallel demodulators operating at half the original sampling rate, thereby reducing the processing burden on individual hardware components while maintaining the ability to handle high bandwidth signals through the combined parallel processing capability
2Adaptability or versatility
If the ADC sampling rate is increased to handle high bandwidth signals, then the signal bandwidth capability is improved, but the power consumption increases
Solution Approach 1:
The patent segments the processing of high-rate samples into two parallel lower-rate processing paths. By operating demodulators and filters at half the original sampling rate (fADC/2), each processing stage consumes less power individually, and the overall system achieves the required bandwidth handling capability through the combined output of both parallel paths without the power penalty of a single high-rate processing chain
3Adaptability or versatility
If the ADC sampling rate is increased to handle high bandwidth signals, then the signal bandwidth capability is improved, but the hardware cost increases
Solution Approach 1:
The patent segments the high-rate processing task into two parallel lower-rate processing chains. This segmentation allows the use of less complex, lower-cost hardware components for each processing path while achieving the overall high bandwidth capability through parallel operation. The reduced sampling rate (fADC/2) for each path enables the use of more economical hardware implementations compared to a single high-rate processing system
4Adaptability or versatility
If the ADC sampling rate is increased to handle high bandwidth signals, then the signal bandwidth capability is improved, but the processing requirements increase
Solution Approach 1:
The patent segments the processing workload by dividing the high-rate sample stream into even and odd samples that are processed in parallel at half the original rate. This segmentation reduces the processing requirements for each individual processing stage while maintaining the overall system capability to handle high bandwidth signals through the combined parallel processing of both streams
Solution Approach 2:
The patent employs periodic action by using two parallel processing paths that operate alternately on even and odd samples respectively. Each path processes samples at a reduced periodic rate (fADC/2), and their combined output reconstructs the full high-rate signal processing capability, thereby reducing the instantaneous processing requirements of any single path
Data Source
AI summary
A superheterodyne receiver includes an A/D converter for converting an IF signal to a stream of samples at a sampling frequency that is four times the IF and a splitter that splits the stream of samples into a first set of even samples and a second set of odd samples. A first quadrature demodulator demodulates just the first set of even samples to produce one of real (I) and imaginary (Q) components of a complex signal at one half of the sampling frequency, and a second, parallel quadrature demodulator demodulates just the second set of odd samples to produce the other of the I and Q components. The demodulated first set is filtered using a first subset of filter coefficients, and the demodulated second set is filtered using a second subset of filter coefficients. The filter outputs correspond to a baseband complex signal. The technology disclosed reduces overall hardware complexity and operating frequency by a factor of two or more.