Parallel IGBT Current Sharing via Periodic Switching

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Solution Overview

Problem

Existing technologies face challenges in achieving ideal current sharing between paralleled IGBTs, leading to reduced thermal efficiency and capacity utilization due to unequal current distribution, especially in high-speed switching applications, which affects the performance of inverters and motor systems.

Innovation Solution

Implementing an alternate switching pattern where each IGBT in a pair is turned on every other pulse, ensuring equal average current flow and reduced losses, thereby maximizing capacity and minimizing thermal stress without requiring physical symmetry in busbar connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If direct paralleling of IGBTs is used to handle higher current, then current handling capacity is improved, but current sharing between paralleled IGBTs becomes unequal leading to reduced capacity utilization

Engineering Contradiction:
Improvecurrent handling capacityVSAvoidcapacity utilization
Core Design Contradiction:
PowerVSProductivity

Solution Approach 1:

The patent applies periodic action by alternately switching the paralleled IGBTs in a cyclic manner. Instead of simultaneously switching all paralleled IGBTs, the controller switches them in alternating sequences, ensuring that each IGBT conducts for equal average time periods. This periodic switching pattern equalizes the average current through each device, resolving the current sharing inequality problem while maintaining high current handling capacity.

Inventive Principle:
Principle #19Periodic action

2Speed

If IGBTs are switched faster to improve switching performance, then switching speed is improved, but dynamic current sharing between paralleled IGBTs becomes more challenging

Engineering Contradiction:
Improveswitching speedVSAvoiddynamic current sharing
Core Design Contradiction:
SpeedVSEase of operation

Solution Approach 1:

The periodic alternating switching scheme naturally accommodates high switching speeds by establishing a regular switching pattern. The controller alternates between paralleled IGBTs at high frequencies, and the periodic nature of this switching ensures that dynamic effects average out over each cycle, maintaining equal current distribution even at high switching speeds.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent employs dynamics by implementing a dynamic switching control strategy that adapts to the high-speed operation of modern IGBTs. The controller dynamically alternates between paralleled devices, adjusting switching timing to ensure equal average current sharing despite variations in individual device characteristics and high switching frequencies.

Inventive Principle:
Principle #15Dynamics

3Temperature

If paralleled IGBTs are used to reduce thermal stress, then thermal stress on individual devices is reduced, but unequal current sharing causes thermal runaway risks

Engineering Contradiction:
Improvethermal stressVSAvoidthermal runaway resistance
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The periodic alternating switching pattern ensures that each paralleled IGBT conducts for equal average time periods, which equalizes the average power dissipation and heat generation across all paralleled devices. This prevents any single device from overheating and eliminates the thermal runaway risk associated with unequal current sharing, while still benefiting from the reduced thermal stress of parallel configuration.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS9912279B2Circuit with current sharing alternately switched parallel transistors
Publication Date: 2018.03.06 HAMILTON SUNDSTRAND CORP
  • US9912279B2 patent drawing
  • US9912279B2 patent drawing
  • US9912279B2 patent drawing

AI summary

A method of operating parallel connected transistors including a first transistor and a second transistor having their respective collectors and emitters connected together includes receiving a first pulse and providing it for a first time period to a gate of the first transistor and not to the second transistor. The method also includes receiving a second pulse and providing it for a second time period to a gate of the second transistor and not to the first transistor and receiving a third pulse and providing it to the gate of the first transistor and not to the second transistor for the first time period.