Parallel IGBT Gate Circuit for Junction Temperature Balancing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices with multiple power chips in parallel face challenges in managing temperature differences among chips, leading to limited operating temperature ranges due to uneven heat distribution and thermal interference, which affects switching losses and overall efficiency.
Innovation Solution
A semiconductor device configuration with three IGBT chips and free-wheeling diodes, where a gate voltage adjusting circuit with reverse parallel diodes is used to reduce the gate voltage of the chip with the highest junction temperature, thereby reducing its collector current and power loss, and thus minimizing temperature differences among chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple power chips are connected in parallel to increase current capacity, then the device can handle higher power loads, but temperature differences among chips increase due to uneven heat distribution and thermal interference
Solution Approach 1:
The patent applies local quality by providing individual gate resistance adjusting circuits for each IGBT chip, allowing independent control of gate resistance for each chip. This enables localized adjustment of switching characteristics to compensate for temperature differences, with each chip's gate resistance being independently optimized based on its thermal conditions rather than using a uniform approach for all chips.
Solution Approach 2:
The patent changes the gate resistance parameter dynamically for each chip based on its temperature conditions. The gate resistance adjusting circuits modify the gate resistance values to optimize switching performance and reduce temperature differences, transforming a static parameter into a dynamically adjustable one that adapts to thermal conditions.
2Temperature
If gate resistance is adjusted to reduce temperature difference among chips, then temperature uniformity improves, but switching loss varies and the range of temperatures that can be evened out is limited when operating frequency is low
Solution Approach 1:
The patent implements feedback mechanisms where temperature detection circuits monitor the thermal conditions of each chip, and this information feeds back to the gate resistance adjusting circuits. The adjusting circuits then modify gate resistance based on the detected temperature differences, creating a closed-loop control system that continuously optimizes temperature uniformity while managing switching losses.
Solution Approach 2:
The patent introduces dynamic adjustment of gate resistance that adapts to real-time temperature conditions. Rather than using fixed resistance values, the system dynamically modifies gate resistance parameters based on detected temperature differences, enabling the system to respond adaptively to changing thermal conditions and operate effectively across a broader temperature range.
3Temperature
If individual gate voltage adjustment circuits are provided for each chip to optimize temperature distribution, then temperature control precision improves, but device complexity increases
Solution Approach 1:
The patent merges multiple gate resistance adjusting circuits into a unified control architecture where similar circuit blocks are used across chips. By combining temperature detection functions and using standardized adjusting circuit designs, the system achieves individual chip control while reducing overall complexity through modularization and functional integration.
Solution Approach 2:
The patent employs universal gate resistance adjusting circuits that can be applied to each chip with the same basic design. These multi-functional circuits serve both temperature compensation and switching optimization purposes, reducing the need for separate specialized circuits for each function and thereby simplifying the overall device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the junction temperature difference among semiconductor chips, enhances efficiency by lowering power losses, and simplifies the device design without requiring complex control circuits or individual gate voltage adjustments for each chip.
Implementation Method 1
a gate voltage adjusting circuit including a first diode having an anode electrically connected to a gate pattern and a cathode electrically connected to a gate of the second semiconductor chip and a second diode connected in reverse parallel with the first diode
Data Source
AI summary
A semiconductor device including a first semiconductor chip, a second semiconductor chip, the junction temperature of which becomes higher than that of the first semiconductor chip during switching of the semiconductor device, a collector pattern electrically connected to a collector of the first semiconductor chip and a collector of the second semiconductor chip, an emitter pattern electrically connected to an emitter of the first semiconductor chip and an emitter of the second semiconductor chip, a gate pattern electrically connected to a gate of the first semiconductor chip, a first diode having an anode electrically connected to the gate pattern and a cathode electrically connected to a gate of the second semiconductor chip and a second diode connected in reverse parallel with the first diode.