Parallel IJTAG Bus Architecture for Scan Bandwidth Bottlenecks
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Solution Overview
Problem
The low speed and serial nature of existing IJTAG scan networks in semiconductor devices becomes a bottleneck as the complexity and diagnostic data increase, limiting test time and bandwidth, especially in hierarchical designs with numerous functional units.
Innovation Solution
Implementing a data streaming network with configurable interface devices and multiplexing/pipeline devices that allow parallel data transmission, coupled with a high-speed parallel bus to enhance bandwidth, and employing time slot multiplexing and clock stretching techniques to optimize data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a serial IJTAG scan network is used to access functional units, then the network structure is simple and compatible with existing standards, but the bandwidth is low and test time increases
Solution Approach 1:
The patent divides the scan network into multiple independent scan chains that can operate simultaneously. Each scan chain can be configured to access different functional units in parallel, effectively segmenting the single serial access path into multiple concurrent access paths, thereby increasing overall test throughput without requiring a completely new network architecture
Solution Approach 2:
The patent transitions from a single-dimensional serial access sequence to a multi-dimensional parallel access structure by introducing multiple scan chains that operate concurrently. This dimensional expansion allows simultaneous testing of multiple functional units, converting the time-sequential serial protocol into a space-parallel architecture that maintains compatibility with existing IJTAG standards while dramatically improving test speed
2Speed
If clock stretching or pipeline stages are added to increase shift speed, then the shift speed reaches low 100 MHz range, but the bandwidth is still orders of magnitude lower than needed due to serial nature and two edge timing
Solution Approach 1:
The patent merges multiple scan chains into a unified parallel scanning architecture where multiple data streams are transmitted simultaneously through different chains. This combining of parallel paths creates a composite bandwidth that is the sum of individual chain bandwidths, achieving orders of magnitude improvement over single-chain serial approaches while maintaining coordinated control through a central controller
Solution Approach 2:
The patent implements dynamic configuration of scan chains where the controller can selectively activate different chains based on test requirements. The system dynamically adjusts which chains are active and their timing relationships, allowing flexible optimization of bandwidth for different test scenarios while maintaining compatibility with existing IJTAG timing protocols
3Productivity
If multi-chain scan interfaces are used to increase bandwidth, then the bandwidth improves, but the routing across physical block boundaries becomes costly and messy and incompatible with modern core-based design flows
Solution Approach 1:
The patent introduces a central controller as an intermediary that manages the coordination between multiple scan chains. This controller acts as a mediator that abstracts the complexity of multi-chain routing from the physical layout, providing a centralized interface for configuring and controlling parallel scan operations. The controller handles the routing decisions and timing coordination, shielding the physical blocks from routing complexity while enabling high bandwidth operation
Data Source
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AI summary
High Bandwidth IJTAG Through High Speed Parallel Bus A system in a circuit comprises: a first network (710) configurable to transmit data in parallel in the circuit, the first network (710) comprising circuit block interface devices, each of the circuit block interface devices being coupled to ports of one of circuit blocks in the circuit; a plurality of second networks (720, 725, 727), each of the plurality of second networks (720, 725, 727) configurable to transmit data in serial in one of the circuit blocks in the circuit; a third network (730) configurable to transmit data in serial in the circuit when being coupled to the plurality of second networks (720, 725, 727); and a plurality of network switching interface devices (740, 745, 747), each of the plurality of network switching interface devices (740, 745, 747) configurable to couple either the first network (710) or the third network (730) to one of the plurality of second networks (720, 725, 727) based on a control signal stored in the each of the plurality of interface devices (740, 745, 747).