Parallel Image Compression Circuits for High-Speed Processing

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Solution Overview

Problem

Current image processing technologies face challenges in achieving high-speed image compression, leading to longer processing times and increased costs due to the need for dedicated image sensors and inefficient scaling factor prediction and updating.

Innovation Solution

An image processing device with multiple image compression processing circuits and a compression control part that performs parallel processing and adjusts compression conditions to optimize compression data alignment and storage, allowing for faster image compression and reduced costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a single image compression processing circuit is used, then device complexity is reduced, but processing speed becomes insufficient because compression processing is heavier than interpolation processing

Engineering Contradiction:
Improveimage compression processing speedVSAvoidnumber of compression processing circuits
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The image compression processing is divided into multiple independent compression processing circuits (first compression processing circuit and second compression processing circuit). Each circuit processes different image data in parallel, thereby increasing overall processing speed while keeping each individual circuit relatively simple in structure

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple compression processing circuits are combined to work simultaneously on different image data. The circuits are merged into a unified system that processes multiple frames or different processing units of images in parallel, achieving high-speed compression without requiring overly complex individual circuits

Inventive Principle:
Principle #5Merging (Combining)

2Speed

If dedicated image sensors are used for parallel processing, then processing speed is improved, but device cost increases

Engineering Contradiction:
Improveparallel processing speedVSAvoiddevice cost
Core Design Contradiction:
SpeedVSEase of manufacture

Solution Approach 1:

A single image sensor is designed to output multiple types of signals (first signal and second signal) that can be used for different processing purposes. This multi-functional approach eliminates the need for separate dedicated sensors for each processing path, reducing device cost while maintaining parallel processing capability

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The image sensor's output parameters are changed to provide multiple signal types simultaneously. By adjusting the sensor's operational parameters and signal output characteristics, the system achieves parallel processing functionality without adding expensive dedicated sensors

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If fixed length compression is used, then remaining frame count can be easily determined, but processing time increases due to heavier compression processing

Engineering Contradiction:
Improveremaining frame count determinationVSAvoidcompression processing time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The system performs partial compression processing on multiple images simultaneously using multiple compression circuits. By processing only portions of images in parallel rather than completing full compression of one image sequentially, the system reduces overall processing time while still providing sufficient compression data to determine remaining frame counts

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS8249339B2Image processing device and electronic camera
Publication Date: 2012.08.21 NIKON CORP
  • US8249339B2 patent drawing
  • US8249339B2 patent drawing
  • US8249339B2 patent drawing

AI summary

An image processing device includes an interpolation color processing circuit receiving images of continuous frames to perform interpolation and color processing thereon, a storage part cyclically storing a plurality of frames of images being processed and having been processed by the interpolation color processing circuit, a plurality of image compression processing circuits reading the images of frames processed by the interpolation color processing circuit to perform image compression processing on the images and being cyclically started up for each of frames to perform parallel processing, and a compression data storage part storing compression data processed by the image compression processing circuit. The image processing device can solve a problem of a prior art in that long processing time is required because image compression processing is heavier than interpolation processing and color processing.