Parallel Image Decoding in Thin Client GPU Cores
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Solution Overview
Problem
Traditional network-based computer architectures face inefficiencies due to underutilization of resources and complex management, particularly in thin client or zero client systems that rely heavily on centralized servers for computing power, leading to slower image processing and asset management challenges.
Innovation Solution
A computing device with a processor, multiple graphic processing cores, RAM, non-volatile memory, and a display processing unit, configured to communicate with a virtual machine and decode encoded image frames in parallel, utilizing a virtual desktop client to generate and transmit display signals efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a thin client uses a centralized server for computing power, then the device complexity is reduced, but the processing speed deteriorates
Solution Approach 1:
The patent segments the image processing task by dividing the image into multiple tiles and assigning each tile to a separate graphics processing core for parallel decoding. This segmentation allows the thin client to maintain low device complexity while improving processing speed through concurrent execution of multiple decoding operations.
Solution Approach 2:
The patent introduces a new dimension of parallelism by utilizing multiple graphics processing cores simultaneously to decode different image tiles. This dimensional approach to processing enables the system to maintain simplicity while achieving high processing throughput.
2Device complexity
If a thin client processes image frames sequentially, then the device complexity is low, but the processing time increases
Solution Approach 1:
The patent segments the image frame into multiple tiles and distributes them across multiple graphics processing cores for parallel decoding. This segmentation enables simultaneous processing of multiple image portions, significantly reducing total processing time while maintaining acceptable device complexity.
Solution Approach 2:
The patent ensures continuous useful action by having multiple graphics processing cores decode different image tiles concurrently. This parallel approach eliminates idle time between decoding operations and maintains continuous progress on the entire image frame processing task.
3Productivity
If multiple graphics processing cores are used for parallel decoding, then the processing efficiency is improved, but the device complexity increases
Solution Approach 1:
The patent segments the decoding task across multiple graphics processing cores, with each core responsible for specific image tiles. This segmentation strategy improves processing efficiency through parallelism while keeping the overall system architecture manageable by assigning clear, independent responsibilities to each core.
Solution Approach 2:
The patent implements a universal approach where multiple graphics processing cores perform the same decoding function on different data portions. This multi-functionality allows the system to achieve high processing efficiency without requiring specialized hardware for each processing stage, thereby limiting the increase in device complexity.
Data Source
AI summary
Disclosed herein is a computing device that includes: a processor; a graphic processing unit having N graphic processing cores, N being an integer greater than 1; a random access memory (RAM); a video port; a non-volatile memory, and a display processing unit. The non-volatile memory stores a virtual desktop client (VDC). The VDC can communicate with a first virtual machine (VM) of a hypervisor running on a remote computing device and receive an encoded image frame from the first VM; instruct the plurality of graphic processing cores to decode the encoded image frame in parallel; and generate a decoded image frame of the encoded image frame. The display processing unit can generate display signals representing the decoded image frame and transmit the display signals to the video port.