Image Encoding Chip Architecture for Parallel Memory-Based Processing
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Solution Overview
Problem
Conventional image processing systems experience idle times and inefficient resource utilization due to time division multiplexing, leading to degraded performance and complex resource allocation.
Innovation Solution
An image processing chip with a processing circuit, encoder, and external memory that utilizes registers and encoding circuits to manage data transfer and encoding operations, reducing idle times by storing preparation data in external memory and enabling simultaneous processing of multiple tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional TDM encodes two groups of image data alternately using the same hardware resource, then hardware resource utilization is improved, but idle time increases and performance degrades
Solution Approach 1:
The patent divides the encoding hardware into two independent encoders (first encoder and second encoder), allowing simultaneous encoding of two image data groups. This segmentation eliminates the idle time caused by sequential processing while maintaining hardware resource utilization through dedicated parallel processing units.
Solution Approach 2:
The patent transitions from single-dimensional sequential processing to two-dimensional parallel processing by introducing a second encoder that operates simultaneously with the first encoder. This dimensional change enables concurrent encoding of multiple image data groups, eliminating idle time while maintaining resource utilization.
2Reliability
If resource locks are used to prevent different tasks from using the same hardware at the same time, then data consistency is improved, but software complexity increases and resource allocation becomes uneven
Solution Approach 1:
The patent extracts the resource locking mechanism from the software layer and replaces it with dedicated hardware resources (two independent encoders). This eliminates the need for complex resource lock management in software while maintaining data consistency through hardware-level isolation of encoding tasks.
Solution Approach 2:
The patent introduces an address generator and address register as intermediaries that manage data flow between the processing circuit and encoders without requiring resource locks. These intermediary components coordinate access to external memory, ensuring data consistency while simplifying software complexity by removing lock management requirements.
3Reliability
If software waits for hardware to finish encoding before transferring the next task, then data consistency is improved, but productivity decreases due to idle time
Solution Approach 1:
The patent implements preliminary action by having the address generator prepare the next encoding task's address information in advance and load it into the address register during the current encoding operation. This allows the processing circuit to immediately transfer the next task to the available encoder without waiting, maintaining data consistency through pre-prepared address information while maximizing productivity through continuous processing.
Data Source
AI summary
An image processing chip is coupled to an external memory and includes a processing circuit and an encoder. The processing circuit is configured to write data to be encoded into a memory address of the external memory. The encoder includes first and second registers, a data input circuit, and an encoding circuit. The first register is configured to store the memory address under control of the processing circuit. The data input circuit is configured to read the data to be encoded from the external memory according to the memory address in the first register and write the data to be encoded into the second register. The encoding circuit is configured to perform an encoding operation according to the data to be encoded in the second register to generate encoded data. The encoder stores the encoded data or an output data derived from the encoded data in the external memory.