Parallel Image Encoding with Processor-Coprocessor Band Assignment

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Solution Overview

Problem

Existing video encoding techniques face challenges in achieving real-time high-quality processing, particularly for high-resolution videos, due to limitations in parallelization methods that restrict compression efficiency and require complex, costly multi-processor architectures, where the number of processors and coprocessors often do not match, leading to suboptimal performance and increased costs.

Innovation Solution

A method for encoding or decoding images using a distributed set of processors and coprocessors, where processors and coprocessors are assigned to contiguous bands of blocks, with specific message rules for synchronization, allowing for optimal parallelization and preservation of spatial and temporal dependencies, even when the number of processors differs from the number of coprocessors, thereby enhancing compression performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If video encoding is performed using a single processor sequentially processing all blocks, then spatial dependencies between blocks are preserved, but computing time becomes excessively long and real-time processing is not achieved

Engineering Contradiction:
Improvecomputing timeVSAvoidparallelization complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The image is divided into multiple vertical bands, with each band containing multiple blocks. Processors are assigned to process specific bands in parallel, breaking the sequential processing bottleneck while maintaining dependency constraints through controlled message passing between processors.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from one-dimensional sequential processing to two-dimensional parallel processing by introducing vertical band segmentation. This allows multiple processors to work simultaneously on different spatial regions while maintaining causal dependencies through message exchange protocols.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If the number of processors is increased to reduce computing time, then real-time processing capability is improved, but system cost and architectural complexity increase significantly

Engineering Contradiction:
Improvereal-time processing capabilityVSAvoidmulti-processor architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system segments the image into vertical bands that can be processed by multiple processors simultaneously. This segmentation allows scalable parallelization where the number of processors can be adjusted based on performance requirements without fundamentally changing the architectural approach.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Message passing serves as an intermediary mechanism that coordinates between processors and coprocessors. This abstraction layer simplifies the complexity of inter-processor communication by providing standardized protocols for data exchange and dependency management.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If slices are used to enable parallel processing of image portions, then computing time is reduced, but compression efficiency deteriorates due to loss of inter-slice spatial correlation

Engineering Contradiction:
Improveparallel processing capabilityVSAvoidcompression efficiency
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

Instead of slicing horizontally across the entire image, the patent segments vertically into bands that process blocks in their natural sequential order within each band. This vertical segmentation allows parallel processing of multiple bands while preserving the spatial correlation needed for efficient compression within each band.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each processor handles a specific vertical band with local processing optimization, maintaining the spatial dependencies within that band. This local quality approach ensures that compression efficiency is preserved within each processing unit while achieving parallel speedup across multiple units.

Inventive Principle:
Principle #3Local quality

4Device complexity

If processors and coprocessors are used with mismatched numbers, then hardware cost is reduced, but processing performance becomes suboptimal

Engineering Contradiction:
Improvehardware costVSAvoidprocessing performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The message passing protocol provides a universal interface that works regardless of the number of processors or coprocessors. This multi-functionality allows the system to accommodate mismatched numbers of processing units while maintaining optimal performance through flexible task distribution and synchronization.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8111749B2Image encoding or decoding method and device, with parallelization of processing over several processors and coprocessors, corresponding computer-readable storage medium
Publication Date: 2012.02.07 MK SYST USA INC
  • US8111749B2 patent drawing
  • US8111749B2 patent drawing
  • US8111749B2 patent drawing

AI summary

A method is proposed for encoding/decoding an image having rectangular blocks of pixels. The image has a height of H blocks and a width of W blocks and is divided into vertical (or horizontal) bands of blocks having the height of H (or width of W) blocks. The method includes: obtaining N processors and M coprocessors, the M coprocessors distributed over S levels, N>1, S>0 and M>S; assigning the N processors Pi to N contiguous bands BPi having sizes of Ki blocks, 0≦i≦N−1 and∑i=0N-1⁢⁢Ki=W;for every level of coprocessors s, 0≦s≦S−1, assigning Ms coprocessors CPs,j to Ms contiguous bands having sizes of Qs,j blocks, with:∑j=0Ms-1⁢⁢Qs,j=W;managing sending of first, second and third start messages, and first and second verification messages to the processors and coprocessors, according to a predetermined set of rules.