Parallel Image Processor Halftone Processing Delay Mechanism
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Solution Overview
Problem
Conventional image processing methods, particularly those using the error diffusion algorithm for halftone processing, face challenges in achieving high-speed processing due to complex circuitry and long processing times, especially when handling packed pixel data, which requires rearrangement and input into image processing units.
Innovation Solution
An image processor with parallel processing units, intermediate value calculating units, and retention units that synchronize operations with a clock signal to perform halftone processing on packed image data, delaying the conversion of pixel data until intermediate values are calculated, allowing for parallel processing and efficient error diffusion across pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If error diffusion algorithm is used for halftone processing, then image quality is improved, but processing time increases
Solution Approach 1:
The image processing is divided into multiple scan line processing units that operate in parallel. Each processing unit handles a specific scan line independently, allowing simultaneous processing of multiple lines. This segmentation enables the computationally intensive error diffusion algorithm to be executed parallelly, maintaining high image quality while reducing overall processing time.
Solution Approach 2:
Pixel data for multiple scan lines are stored in advance in a buffer memory before processing begins. This preliminary storage allows the parallel processing units to immediately begin error diffusion calculations without waiting for data input, optimizing the processing pipeline and reducing idle time while maintaining algorithm accuracy.
2Ease of operation
If packing data is used for image processing, then data handling is simplified, but processing speed decreases due to rearrangement requirements
Solution Approach 1:
The patent processes pixel data in the vertical dimension (scan line direction) through parallel processing units, while maintaining the horizontal packing structure within each line. This dimensional approach allows packing data to be processed without complete rearrangement, as each scan line's packed pixels are handled independently and simultaneously with other lines, preserving both data handling simplicity and processing speed.
3Productivity
If multiple image processing units are provided for parallel processing, then processing speed is improved, but device complexity increases
Solution Approach 1:
Multiple processing units are designed with identical, standardized architectures that can handle any scan line. Each unit contains the complete error diffusion logic and can process pixels from any position in the image. This universal design allows parallel processing speedup while controlling complexity through repetition of a single, well-defined processing module rather than creating specialized circuits for each function.
Data Source
AI summary
Provided is an image processor obtaining image data divided in packing units, comprising: a parallel processing unit performing an image conversion processing in parallel on the pixel data arranged in a sub scan direction in the packing unit, based on the obtained pixel data and the intermediate value for the pixel data, to calculate an output value after the conversion of the pixel data and an index value; an intermediate value calculating unit calculating an intermediate value based on the respective index values calculated by the parallel processing units regarding pixels within a predetermined relative position range; and a first retention unit for delaying the start of the image conversion processing to one pixel data for a delay period set to be equal to or longer than a period required for obtaining the one pixel data and calculating the intermediate value for the one pixel data.